US2007184644A1PendingUtilityA1

Ball grid array copper balancing

46
Assignee: INTEL CORPPriority: Jun 30, 2003Filed: Mar 26, 2007Published: Aug 9, 2007
Est. expiryJun 30, 2023(expired)· nominal 20-yr term from priority
H10W 70/65H10W 90/701
46
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Claims

Abstract

A ball grid array device includes a substrate having a first major surface and a second major surface. The first major surface includes leads for electrical connections. The second major surface is devoid of leads. The ball grid array device also includes a first land having a solder mask opening at the first major surface of the substrate, and a second, buried land near the first major surface of the substrate. A method for forming an electronic device includes forming an electronic circuit in a substrate, placing an input pad for an input to the electronic circuit on at least one major surface of the substrate, placing an output pad for an output from the electronic circuit on the at least one major surface of the substrate, and placing an electrically isolated pad near the at least one major surface of the substrate.

Claims

exact text as granted — not AI-modified
1 . A method for forming an electronic device comprising: 
 forming an electronic circuit in a substrate;    placing an input pad for an input to the electronic circuit on at least one major surface of the substrate;    placing an output pad for an output from the electronic circuit on the at least one major surface of the substrate; and    placing an electrically isolated pad near the at least one major surface of the substrate.    
   
   
       2 . The method of  claim 1  wherein the input pad, the output pad and the isolated pad are positioned in a pattern.  
   
   
       3 . The method of  claim 1  further comprising placing a via near the isolated pad.  
   
   
       4 . The method of  claim 1  further comprising attaching a via to the isolated pad, the via and the isolated pad being electrically isolated.  
   
   
       5 . A method for forming an electronic device comprising: 
 forming an electronic circuit in a substrate;    placing a plurality of input pads for inputting signals to the electronic circuit on at least one major surface of the substrate;    placing a plurality of output pads for receiving outputs from the electronic circuit on the at least one major surface of the substrate; and    placing a plurality of electrically isolated pads near the at least one major surface of the substrate.    
   
   
       6 . The method of  claim 5  wherein the plurality of input pads, the plurality of output pads, and the plurality of electrically isolated pads form an array.  
   
   
       7 . The method of  claim 5  wherein the plurality of input pads and the plurality of output pads form an array having at least one void therein, and wherein the plurality of electrically isolated pads are placed to complete the array.  
   
   
       8 . The method of  claim 5  wherein the plurality of input pads, the plurality of output pads, and the plurality of electrically isolated pads form an array of equally spaced metal portions in a matrix of a second material.

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