Semiconductor device having sufficient process margin and method of forming same

Abstract

According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.

1 . A method of manufacturing a semiconductor device comprising: 
 providing a substrate doped with a P type impurity;    doping an N type impurity into the substrate to divide the substrate into a P type impurity region and an N type impurity region;    forming active patterns having a first pitch in the P type and N type impurity regions; and    forming gate patterns having a second pitch on the active patterns in a direction substantially perpendicular to the active patterns.    
   
   
       2 . The method of  claim 1 , wherein the first pitch is substantially the same as the second pitch.  
   
   
       3 . The method of  claim 1 , wherein the unit cell region comprises a first side and a second side substantially perpendicular to the first side, and wherein the first side has a length substantially equal to an integral multiple of the first pitch.  
   
   
       4 . The method of  claim 3 , wherein the second side has a length substantially equal to an integral multiple of the second pitch.  
   
   
       5 . A method of manufacturing an SRAM device comprising: 
 doping a substrate with a P type impurity;    doping an N type impurity into the substrate to divide the substrate into a P type well and an N type well;    forming active patterns having a first pitch in the P type and N type wells; and    forming gate patterns having a second pitch on the active patterns in a direction substantially perpendicular to the active patterns.    
   
   
       6 . The method of  claim 5 , wherein the first pitch is substantially identical to the second pitch.  
   
   
       7 . The method of  claim 5 , wherein the unit cell region comprises a first side and a second side substantially perpendicular to the first side, and wherein the first side of the unit cell region has a length substantially equal to an integral multiple of the first pitch.  
   
   
       8 . The method of  claim 7 , wherein the second side of the unit cell region has a length substantially equal to an integral multiple of the second pitch.  
   
   
       9 . The method of  claim 5 , further comprising: 
 forming an insulating interlayer on the active and gate patterns;    etching the insulating interlayer to form contact holes partially exposing surfaces of the active and gate patterns, the contact holes being disposed to have third pitches in an X direction and fourth pitches in a Y direction substantially perpendicular to the X direction, the third pitches substantially equal to an integral multiple of a minimum pitch among the third pitches, and the fourth pitches substantially equal to an integral multiple of a minimum pitch among the fourth pitches; and    filling the contact holes with a conductive layer to form contacts.    
   
   
       10 . The method of  claim 9 , wherein forming the contact holes comprises: 
 forming a photoresist layer on the insulating interlayer;    exposing the photoresist layer using an exposure mask to form a photoresist pattern; and    etching the insulating interlayer using the photoresist pattern as an etching mask.    
   
   
       11 . The method of  claim 10 , wherein the exposure mask comprises contact patterns for forming the contacts and dummy contact patterns disposed between the contact patterns.  
   
   
       12 . The method of  claim 11 , wherein the contact patterns and the dummy contact patterns are uniformly spaced apart from each other.