MOS transistors and methods of manufacturing the same

Abstract

MOS transistors having a low junction capacitance between their halo regions and their source/drain extension regions and methods for manufacturing the same are disclosed. A disclosed MOS transistor includes: a semiconductor substrate of a first conductivity type; a gate insulating layer pattern and a gate on an active region of the substrate; spacers on side walls of the gate; source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure; halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and source/drain regions of the second conductivity type within the substrate on opposite sides of the spacer.

1 . A MOS transistor comprising: 
 a semiconductor substrate of a first conductivity type;    a gate insulating layer pattern and a gate on an active region of the substrate defined by an isolation layer;    spacers on side walls of the gate;    an ion implanting buffer layer between the gate and the spacers;    source/drain extension regions of a second conductivity type within the substrate on opposite sides of the gate, the source/drain extension regions having a graded junction structure;    halo impurity regions of the first conductivity type within the substrate under opposite edges of the gate adjacent respective ones of the source/drain extension regions; and    source/drain regions of the second conductivity type within the substrate on opposite sides of the spacers.    
   
   
       2 . A MOS transistor as defined in  claim 1 , wherein each of the source/drain extension regions includes a first source/drain extension region and a second source/drain extension region under the first source/drain extension region.  
   
   
       3 . A MOS transistor as defined in  claim 2 , wherein the second source/drain extension region has a higher impurity concentration than the first source/drain extension region.  
   
   
       4 . A MOS transistor as defined in  claim 1 , wherein the first conductivity type is an n-type and the second conductivity type is a p-type.  
   
   
       5 . A MOS transistor as defined in  claim 1 , wherein the first conductivity type is a p-type and the second conductivity type is an n-type.  
   
   
       6 . A MOS transistor as defined in  claim 1 , wherein the halo impurity regions has an impurity concentration of about 1×10 14  to 1×10 15  ions/cm 2 .  
   
   
       7 . A MOS transistor as defined in  claim 6 , wherein the impurity comprises boron (B).  
   
   
       8 . A MOS transistor as defined in  claim 1 , wherein the ion implanting buffer layer comprises an oxide layer.  
   
   
       9 . A MOS transistor as defined in  claim 1 , wherein the ion implanting buffer layer is also on part of the active region under the spacer.  
   
   
       10 . A MOS transistor as defined in  claim 1 , wherein the ion implanting buffer layer is also on the gate.  
   
   
       11 . A MOS transistor as defined in  claim 1 , wherein each of the source/drain extension regions has a graded junction structure.  
   
   
       12 . A MOS transistor as defined in  claim 2 , wherein the first source/drain extension region has a concentration of about 5×10 13  to 5×10 14  arsenic (As) ions/cm 2 .  
   
   
       13 . A MOS transistor as defined in  claim 2 , wherein the second source/drain extension region has a concentration of about 1×10 14  to 5×10 15  phosphorus (P) ions/cm 2 .