Carrierless chip package for integrated circuit devices, and methods of making same

Abstract

Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes an integrated circuit chip comprising an exposed backside surface defining a plane, a plurality of wire bonds that are conductively coupled to the integrated circuit chip, each of the plurality of wire bonds being conductively coupled to a conductive exposed portion, a portion of the conductive exposed portion being positioned in the plane defined by the backside surface, and an encapsulant material positioned adjacent the integrated circuit chip and the plurality of wire bonds.

1 . A device, comprising: 
 an integrated circuit chip comprising an exposed backside surface defining a plane;    a plurality of wire bonds that are conductively coupled to said integrated circuit chip, each of said plurality of wire bonds being conductively coupled to a conductive exposed portion having a lowermost surface that is positioned in said plane defined by said backside surface, said lowermost surface of said exposed portion having a generally circular cross-sectional configuration within said plane; and    an encapsulant material positioned adjacent said integrated circuit chip and said plurality of wire bonds, wherein a distance from a side of said integrated circuit chip to a side of said encapsulant material ranges from approximately 0.1-0.4 mm and wherein a distance from said backside surface to a top surface of said encapsulant material ranges from approximately 0.1-0.5 mm.    
   
   
       2 . The device of  claim 1 , wherein said integrated circuit chip comprises at least one of a memory device, a microprocessor and an application specific integrated circuit device.  
   
   
       3 . The device of  claim 1 , wherein said wire bonds are comprised of gold.  
   
   
       4 . The device of  claim 1 , wherein said wire bonds are comprised of aluminum.  
   
   
       5 . The device of  claim 1 , wherein said wire bonds are comprised of copper.  
   
   
       6 . The device of  claim 1 , wherein said exposed conductive portions are comprised of aluminum.  
   
   
       7 . (canceled)  
   
   
       8 . (canceled)  
   
   
       9 . (canceled)  
   
   
       10 . The device of  claim 1 , wherein said encapsulant material comprises an epoxy compound, a molding compound or a liquid encapsulant.  
   
   
       11 . The device of  claim 1 , wherein said encapsulant material has a bottom surface that is substantially positioned in said plane.  
   
   
       12 . The device of  claim 1 , wherein said backside surface is a surface that has been subjected to at least one processing operation after said encapsulant material is formed.  
   
   
       13 . The device of  claim 1 , further comprising a conductive structure that is conductively coupled to said exposed conductive portions.  
   
   
       14 . The device of  claim 13 , wherein said conductive structure comprises a printed circuit board, a silicon interposer, a motherboard, flex tape, or a memory module.  
   
   
       15 . The device of  claim 13 , wherein said integrated circuit chip is conductively coupled to said conductive structure by a plurality of conductive balls.  
   
   
       16 . A device, comprising: 
 an integrated circuit chip comprising an exposed backside surface defining a plane;    a plurality of wire bonds that are conductively coupled to said integrated circuit chip, each of said plurality of wire bonds being conductively coupled to a conductive exposed portion, having a lowermost surface that is positioned in said plane defined by said backside surface, said lowermost surface of said exposed portion having a generally circular cross-sectional configuration within said plane;    an encapsulant material positioned adjacent said integrated circuit chip and said plurality of wire bonds, said encapsulant material comprising a bottom surface that is positioned substantially in said plane, wherein a distance from a side of said integrated circuit chip to a side of said encapsulant material ranges from approximately 0.1-0.4 mm and wherein a distance from said backside surface to a top surface of said encapsulant material ranges from approximately 0.1-0.5 mm; and    a conductive structure that is conductively coupled to said exposed conductive portions.    
   
   
       17 . The device of  claim 16 , wherein said integrated circuit chip comprises at least one of a memory device, a microprocessor and an application specific integrated circuit device.  
   
   
       18 . The device of  claim 16 , wherein said wire bonds are comprised of at least one of gold, aluminum and copper.  
   
   
       19 . The device of  claim 16 , wherein said exposed conductive portions are comprised of aluminum.  
   
   
       20 . (canceled)  
   
   
       21 . (Canceled)  
   
   
       22 . (canceled)  
   
   
       23 . The device of  claim 16 , wherein said conductive structure comprises a printed circuit board, a silicon interposer, a motherboard, flex tape, or a memory module.  
   
   
       24 . The device of  claim 16 , wherein said integrated circuit chip is conductively coupled to said conductive structure by a plurality of solder balls.  
   
   
       25 .- 60 . (canceled)