Transferring data from stacked memory

Abstract

Methods and apparatus to transfer data from a stacked memory are described. In one embodiment, an interconnect may be utilized to transfer data into a buffer from one or more opened memory pages.

1 . An apparatus comprising: 
 logic to generate a first memory access request in response to a cache miss corresponding to a first cache line; and    an interconnect to transfer a first open page of a memory that comprises data corresponding to the first cache line into a buffer before the first page of the memory is closed.    
   
   
       2 . The apparatus of  claim 1 , further comprising a memory controller to open the first page of the memory and close the first opened memory page after all data stored in the first opened memory page is copied to the buffer through the interconnect.  
   
   
       3 . The apparatus of  claim 2 , wherein the memory controller keeps the first page of the memory open during execution of one or more operations corresponding to the first memory access request.  
   
   
       4 . The apparatus of  claim 1 , wherein the interconnect comprises a plurality of vias.  
   
   
       5 . The apparatus of  claim 1 , wherein the first page of the memory comprises data corresponding to at least a second cache line.  
   
   
       6 . The apparatus of  claim 1 , further comprising a cache controller to generate a cache miss signal after the cache miss occurs, wherein the logic generates the first memory access request in response to the cache miss signal.  
   
   
       7 . The apparatus of  claim 1 , wherein the logic generates a second memory access request in response to the cache miss, the second memory access request to cause opening of a second page of the memory.  
   
   
       8 . The apparatus of  claim 7 , wherein the second page of the memory is contiguous with the first page of the memory.  
   
   
       9 . The apparatus of  claim 7 , further comprising a cache controller to generate a cache miss signal after the cache miss occurs, wherein the logic generates the second memory access request in response to the cache miss signal.  
   
   
       10 . The apparatus of  claim 1 , further comprising a first die that comprises the logic and a second die that comprises the memory.  
   
   
       11 . The apparatus of  claim 1 , wherein the buffer comprises a shared or a private cache.  
   
   
       12 . The apparatus of  claim 1 , wherein the buffer comprises a page cache to store the data stored in the first opened memory page prior to copying the data to a cache.  
   
   
       13 . The apparatus of  claim 1 , further comprising one or more processor cores to generate a memory access request that causes the cache miss.  
   
   
       14 . The apparatus of  claim 13 , wherein the one or more processor cores and the logic are on a first die.  
   
   
       15 . The apparatus of  claim 14 , wherein the first die comprises a bulk Si layer, an active Si layer, and a metal stack layer.  
   
   
       16 . The apparatus of  claim 15 , further comprising a heat sink coupled to the bulk Si layer to dissipate heat.  
   
   
       17 . The apparatus of  claim 14 , further comprising a second die that comprises the memory, wherein a plurality of vias couple at least a portion of the first die and at least a portion of the second die.  
   
   
       18 . The apparatus of  claim 17 , wherein the second die comprises a bulk Si layer, an active Si layer, and a metal stack layer.  
   
   
       19 . The apparatus of  claim 17 , wherein the first die and the second die are stacked on each other.  
   
   
       20 . The apparatus of  claim 17 , further comprising one or more through-die vias to couple one or more bumps to one or more of the plurality of vias.  
   
   
       21 . A method comprising: 
 generating one or more memory access requests in response to a cache miss;    opening one or more memory pages corresponding to the one or more memory access requests; and    copying data stored in the one or more opened memory pages to a buffer through a non-shared interconnect.    
   
   
       22 . The method of  claim 21 , further comprising closing the one or more opened memory pages after data stored in the one or more opened memory pages are entirely copied to the buffer.  
   
   
       23 . The method of  claim 21 , wherein opening the one or more memory pages comprises activating one or more rows of a memory.  
   
   
       24 . The method of  claim 21 , wherein copying the data stored in the one or more opened memory pages to the buffer comprises copying the data from a memory to a page cache.  
   
   
       25 . The method of  claim 24 , further comprising copying the data from the page cache to one or more of a shared cache or a private cache.  
   
   
       26 . A system comprising: 
 a memory to store data;    a cache to store data corresponding to at least some of the data stored in the memory;    a first logic to generate a first request for data stored in a first location of the memory and a second request for data stored in a second location of the memory in response to a request for the data stored in the first location; and    a second logic to copy the data stored in the first and second locations into the cache and turn off one or more data storage elements coupled to the first and second locations of the memory after the data stored in the first and second locations is copied into the cache through a non-shared interconnect.    
   
   
       27 . The system of  claim 26 , further comprising one or more processor cores to send the request for data stored in the first location.  
   
   
       28 . The system of  claim 26 , wherein the first location and the second location of the memory are contiguous.  
   
   
       29 . The system of  claim 26 , further comprising a first die that is stacked on a second die, wherein the first die comprises the cache and the first logic and wherein the second die comprises the memory.  
   
   
       30 . The system of  claim 26 , further comprising an audio device.