Structure and method of three dimensional hybrid orientation technology

Abstract

A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. In use, the device includes a nFET stack on a substrate using a first plane and direction, e.g., (100)<110> and a pFET stack on the substrate using a second plane and direction, e.g., (111)/<112>. An isolation region within the substrate is provided between the nFET stack and the pFET stack.

1 . A method of manufacturing a semiconductor structure, comprising forming a first structure from a poly layer on a substrate using a first plane and direction and forming a second structure from the poly layer on the substrate using a second plane and direction.  
   
   
       2 . The method of  claim 1 , wherein the first structure is a stack for a nFET and the second structure is a stack for a pFET.  
   
   
       3 . The method of  claim 1 , wherein the first plane and direction differ from the second plane and direction and the first structure and the second structure are formed simultaneously.  
   
   
       4 . The method of  claim 3 , wherein the first plane and direction is (100)/<110> and the second plane and direction is (111)/<112>.  
   
   
       5 . The method of  claim 1 , wherein forming the second structure on the substrate using a second plane and direction comprises etching the substrate to form an angled sidewall and building the second structure at least partially on the angled sidewall.  
   
   
       6 . The method of  claim 5 , wherein forming the angled sidewall comprises an anisotropic etching of the substrate at an active area of a pFET.  
   
   
       7 . The method of  claim 5 , wherein forming the angled sidewall comprises etching the substrate to result in an angled of approximately 57.5 degrees from a plane of the substrate.  
   
   
       8 . The method of  claim 5 , wherein the forming of the angled sidewall comprises etching through an oxide layer deposited over the substrate, a block material deposited over the oxide layer and into the substrate.  
   
   
       9 . The method of  claim 8 , further comprising: 
 etching a photoresist deposited over the block material,    performing a selective etch of the block material using the oxide layer as a etch stop layer to form an etched area;    stripping the photoresist layer;    forming a spacer in the etched area; and    anisotropic etching the substrate to a depth of approximately 200 Å to 900 Å to form a trench in the substrate which has the angled sidewall.    
   
   
       10 . The method of  claim 1 , wherein forming the first structure and the second structure comprises: 
 forming at least one n-well and one p-well for pFET and nFET devices, respectively;    depositing a gate dielectric on a surface of the substrate including in a trench with an angled sidewall with respect to a plane of the surface of the substrate, the trench is formed in an active area of the pFET;    depositing the poly layer over the gate dielectric;    etching portions of the poly layer to form a nFET stack comprising the first structure on a plane of the substrate and a pFET stack comprising the second structure on the angled sidewall of the trench;    forming spacers on sidewalls of the nFET stack and the pFET stack; and    doping source and drain regions in the substrate for nFET and pFET devices on sides of the nFET stack and the pFET stack, respectively.    
   
   
       11 . The method of  claim 10 , wherein the pFET stack and the nFET stack are in a (111) plane and a <112> direction and in a (100) plane and <110> direction.  
   
   
       12 . A method of manufacturing a semiconductor device, comprising: 
 building a nFET stack on a gate dielectric layer on a substrate in a first plane and direction;    building a pFET stack on the gate dielectric layer on the substrate in a second plane and direction, which is different from the first plane and direction; and    providing an isolation region within the substrate between the nFET stack and the pFET stack.    
   
   
       13 . The method of  claim 12 , wherein the first plane and direction is (100)/<110> and the second plane and direction is (111)/<112>.  
   
   
       14 . The method of  claim 12 , wherein forming the pFET stack comprises etching the substrate to form a trench with an angled sidewall and building the pFET stack at least partially on the angled sidewall.  
   
   
       15 . The method of  claim 14 , wherein forming the angled sidewall comprises anisotropic etching of the substrate using basic wet chemicals at an active area of a pFET.  
   
   
       16 . The method of  claim 14 , wherein the angled sidewall is etched at an angle of approximately 57.5 degrees from a plane of the substrate.  
   
   
       17 . The method of  claim 14 , wherein the forming of the angled sidewall comprises: 
 etching through an oxide layer deposited over the substrate, a block material deposited over the oxide layer using the oxide layer as a etch stop layer to form an etched area;    stripping a photoresist deposited over the block material after etching the block material,    forming a spacer in the etched area; and    anisotropic etching the substrate using wet chemicals to a depth of approximately 200 Å to 900 Å to form the trench in the substrate having the angled sidewall.    
   
   
       18 . The method of  claim 14 , wherein forming the nFET stack and the pFET stack comprises: 
 forming at least one n-well and one p-well for pFET and nFET, respectively;    depositing the gate dielectric layer on a surface of the substrate including in the trench with an angled sidewall with respect to a plane of the surface of the substrate, the trench being formed in an active area of the pFET;    depositing a poly layer over the gate dielectric layer;    etching portions of the poly layer to form the nFET stack and the pFET stack on the angled sidewall of the trench using an isolation region as a basis for alignment;    forming spacers on sidewalls of the nFET stack and the pFET stack;    implanting extensions in the substrate on the side of the nFET stack and the pFET stack; and    doping source and drain regions in the substrate for nFET and pFET on sides of the nFET stack and the pFET stack, respectively.    
   
   
       19 . A method of manufacturing a semiconductor structure, comprising: 
 depositing a gate dielectric layer on a substrate;    depositing a poly layer on the gate dielectric layer on the substrate; and    forming a nFET structure from the poly layer on the gate dielectric layer on the substrate in a first plane and direction; and    forming a pFET structure from the poly layer on the gate dielectric layer on the substrate in a second plane and direction, which is different from the first plane and direction.    
   
   
       20 . The method of  claim 19 , wherein the nFET structure and the pFET structure are formed simultaneously.