Junction barrier schottky rectifiers having epitaxially grown p+-n junctions and methods of making

Abstract

A junction barrier Schottky (JBS) rectifier device and a method of making the device are described. The device comprises an epitaxially grown first n-type drift layer and p-type regions forming p + -n junctions and self-planarizing epitaxially over-grown second n-type drift regions between and, optionally, on top of the p-type regions. The device may include an edge termination structure such as an exposed or buried P + guard ring, a regrown or implanted junction termination extension (JTE) region, or a “deep” mesa etched down to the substrate. The Schottky contact to the second n-type drift region and the ohmic contact to the p-type region together serve as an anode. The cathode can be formed by ohmic contact to the n-type region on the backside of the wafer. The devices can be used in monolithic digital, analog, and microwave integrated circuits.

1 . A semiconductor device comprising: 
 a substrate layer comprising a semiconductor material of a first conductivity type;    an optional buffer layer comprising a semiconductor material of the first conductivity type on the substrate layer,    a drift layer on the substrate layer or buffer layer, the drift layer comprising a semiconductor material of the first conductivity type;    a central region comprising a plurality of regions of semiconductor material of a second conductivity type different than the first conductivity type on a central portion of the drift layer, the regions of semiconductor material of the second conductivity type having upper surfaces and sidewalls; and    an epitaxially over-grown drift region of semiconductor material of the first conductivity on the drift layer adjacent the plurality of regions of semiconductor material of the second conductivity type and, optionally, on upper surfaces of the plurality of regions of semiconductor material of the second conductivity type.    
   
   
       2 . The device of  claim 1 , wherein the regions of semiconductor material of the second conductivity type comprise a plurality of spaced elongate segments having first and second opposed ends.  
   
   
       3 . The device of  claim 1 , wherein semiconductor material of the first conductivity type is on the upper surfaces of the plurality of regions of semiconductor material of the second conductivity type.  
   
   
       4 . The device of  claim 1 , wherein the device comprises the buffer layer.  
   
   
       5 . The device of  claim 4 , wherein the buffer layer has a dopant concentration greater than 1×10 18 /cm 3  and/or a thickness of about 0.5 μm.  
   
   
       6 . The device of  claim 1 , wherein the semiconductor material of the substrate layer, the drift layer, the central region and the drift region is silicon carbide.  
   
   
       7 . The device of  claim 1 , wherein the semiconductor material of the first conductivity type is an n-type semiconductor material and wherein the semiconductor material of the second conductivity type is a p-type semiconductor material.  
   
   
       8 . The device of  claim 1 , wherein the drift layer has a thickness greater than 1 μm.  
   
   
       9 . The device of  claim 1 , wherein the central region has a thickness greater than 0.5 μm.  
   
   
       10 . The device of  claim 1 , wherein the central region has a dopant concentration greater than or equal to 1×10 19 /cm 3 .  
   
   
       11 . The device of  claim 1 , wherein the substrate layer has a dopant concentration greater than 1×10 18 /cm 3 .  
   
   
       12 . The device of  claim 1 , wherein the drift layer and the drift region each have a dopant concentration of 1×10 4 /cm 3  to 1×10 17 /cm 3 .  
   
   
       13 . The device of  claim 1 , wherein the drift region has a different dopant concentration than the drift layer.  
   
   
       14 . The device of  claim 1 , further comprising an ohmic contact material on the substrate opposite the drift layer and an ohmic contact material on the central region.  
   
   
       15 . The device of  claim 2 , wherein the regions of semiconductor material of the second conductivity type further comprise a first bus-bar connecting the first ends of the elongate segments and a second bus-bar connecting the second ends of the elongate segments.  
   
   
       16 . The method of  claim 15 , wherein the first and second bus-bars each have a first width and wherein the raised elongate segments have a second width less than the first width.  
   
   
       17 . The method of  claim 15 , wherein the first and second bus-bars have first and second opposed ends and wherein the first end of the first bus bar is connected to the first end of the second bus-bar by a third bus bar.  
   
   
       18 . The method of  claim 17 , wherein the second end of the first bus bar is connected to the second end of the second bus-bar by a fourth bus bar.  
   
   
       19 . The device of  claim 14 , further comprising a metal layers on the ohmic contact material and a Schottky metal layer in contact with at least a portion of the drift region.  
   
   
       20 . The device of  claim 19 , wherein the metal layer on the ohmic contact material on the central region has a different composition than the Schottky metal layer.  
   
   
       21 . The device of  claim 1 , further comprising an edge termination structure in a peripheral portion of the device.  
   
   
       22 . The device of  claim 21 , further comprising a dielectric layer on the edge termination structure.  
   
   
       23 . The device of  claim 21 , wherein the edge termination structure comprises a region of semiconductor material of the second conductivity type implanted in the drift layer.  
   
   
       24 . The device of  claim 21 , wherein the edge termination structure comprises a mesa edge termination.  
   
   
       25 . The device of  claim 21 , wherein the edge termination structure comprises one or more continuous regions of a semiconductor material of the second conductivity type on the drift layer circumscribing the central region.  
   
   
       26 . The device of  claim 25 , further comprising epitaxially grown semiconductor material of the first conductivity type adjacent the one or more continuous regions of semiconductor material of the second conductivity type circumscribing the central region.  
   
   
       27 . The device of  claim 26 , wherein the epitaxially grown semiconductor material of the first conductivity type is on the one or more continuous regions of semiconductor material of the second conductivity type circumscribing the central region.  
   
   
       28 . An integrated circuit comprising: 
 the semiconductor device of  claim 1;  and    at least one additional electronic power component formed on the substrate layer.    
   
   
       29 . The integrated circuit of  claim 28 , wherein the at least one additional electronic power component is selected from the group consisting of a bipolar junction transistor (BJT), a junction field-effect transistor (JFET), a metal-oxide semiconductor field-effect transistor (MOSFET), a gate turn-off thyristor (GTO) and combinations thereof.  
   
   
       30 . A method of making a semiconductor device comprising: 
 selectively etching through a layer of semiconductor material of a second conductivity type on a drift layer of semiconductor material of a first conductivity type different than the second conductivity type to expose material of the drift layer thereby forming a central region comprising a plurality of regions of semiconductor material of the second conductivity type on the drift layer, the regions of semiconductor material of the second conductivity type having upper surfaces and sidewalls;    epitaxially over-growing a drift region of semiconductor material of the first conductivity type on exposed surfaces of the drift layer adjacent to the regions of semiconductor material of the second conductivity type and on upper surfaces of the regions of semiconductor material of the second conductivity type; and    etching the drift region to expose at least a portion of the upper surfaces of the regions of semiconductor material of the second conductivity type;    wherein the drift layer is on a semiconductor substrate or wherein the drift layer is on a buffer layer comprising a semiconductor material of the first conductivity type and wherein the buffer layer is on the semiconductor substrate.    
   
   
       31 . The method of  claim 30 , wherein the regions of semiconductor material of the second conductivity type comprise a plurality of spaced elongate segments having first and second opposed ends.  
   
   
       32 . The method of  claim 31 , wherein the regions of semiconductor material of the second conductivity type further comprise a first bus-bar connecting the first ends of the elongate segments and a second bus-bar connecting the second ends of the elongate segments.  
   
   
       33 . The method of  claim 32 , wherein the first and second bus-bars have a first width and wherein the raised elongate segments have a second width less than the first width.  
   
   
       34 . The method of  claim 32 , wherein the first and second bus-bars have first and second opposed ends and wherein the first end of the first bus bar is connected to the first end of the second bus-bar by a third bus bar.  
   
   
       35 . The method of  claim 34 , wherein the second end of the first bus bar is connected to the second end of the second bus-bar by a fourth bus bar.  
   
   
       36 . The method of  claim 32 , wherein the first and/or second bus-bars are exposed during etching of the epitaxially grown layer of semiconductor material of the first conductivity type.  
   
   
       37 . The method of  claim 36 , wherein the plurality of spaced elongate segments are not exposed during etching of the epitaxially grown layer of semiconductor material of the first conductivity type.  
   
   
       38 . The method of  claim 30 , further comprising etching through the drift layer and the optional buffer layer, if present, in a peripheral portion of the device to expose the underlying substrate.  
   
   
       39 . The method of  claim 30 , further comprising forming an implanted region of semiconductor material of the second conductivity type in the drift layer in a peripheral portion of the device.  
   
   
       40 . The method of  claim 30 , further comprising forming contacts on the drift region and on a surface of the semiconductor substrate opposite the drift layer.  
   
   
       41 . The method of  claim 40 , wherein forming contacts comprises depositing an ohmic contact material on the central region and on the surface of the semiconductor substrate opposite the drift layer and depositing an electrically conductive metal on the ohmic contact material.  
   
   
       42 . The method of  claim 41 , further comprising depositing a Schottky metal on the drift layer.  
   
   
       43 . The method of  claim 42 , further comprising annealing the contacts before depositing the Schottky metal.  
   
   
       44 . The method of  claim 43 , wherein annealing is conducted at a temperature greater than 900° C.  
   
   
       45 . The method of  claim 42 , wherein the Schottky metal and the electrically conductive metal on the ohmic contact material on the drift region are simultaneously deposited.  
   
   
       46 . The method of  claim 45 , further comprising annealing the contacts on the drift region and on the surface of the semiconductor substrate opposite the drift layer.  
   
   
       47 . The method of  claim 46 , wherein annealing is conducted at a temperature greater than 500° C.  
   
   
       48 . The method of  claim 30 , wherein: 
 selectively etching through the layer of semiconductor material of the second conductivity type forms one or more continuous regions of the semiconductor material of the second conductivity type on the drift layer and circumscribing the regions of semiconductor material of the second conductivity type; and    wherein epitaxially growing a semiconductor material of the first conductivity type on exposed surfaces of the drift layer comprises epitaxially growing semiconductor material of the first conductivity type on the drift layer adjacent the one or more continuous regions of semiconductor material of the second conductivity type.    
   
   
       49 . The method of  claim 30 , wherein the drift layer is on a buffer layer comprising a semiconductor material of the first conductivity type and wherein the buffer layer is on the semiconductor substrate.  
   
   
       50 . A semiconductor device made by the method of  claim 30.