Apparatuses and methods to enhance passivation and ILD reliability

Abstract

Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on and limit or eliminate crack propagation in the devices.

1 . An apparatus comprising: 
 a first bump and a second bump on a surface of a substrate;    a first sidewall structure adjacent to the first bump and on the surface;    a second sidewall structure adjacent to the second bump and on the surface; and    a gap between the first sidewall structure and the second sidewall structure that exposes at least a portion of the substrate surface.    
     
     
         2 . The apparatus of  claim 1 , wherein the substrate comprises a device region and an interconnect region, the interconnect region including a low-k interlayer dielectric material.  
     
     
         3 . The apparatus of  claim 1 , further comprising: 
 an undercut between the first bump and the surface, wherein the undercut is encapsulated by the first sidewall structure.    
     
     
         4 . The apparatus of  claim 1 , wherein the first sidewall structure has a width in the range of about 1 to 15 microns.  
     
     
         5 . The apparatus of  claim 1 , wherein the first sidewall structure comprises silicon nitride.  
     
     
         6 . The apparatus of  claim 1 , wherein the first bump comprises copper.  
     
     
         7 . The apparatus of  claim 1 , further comprising: 
 a contact on a second substrate, wherein the first bump and the contact are electrically connected.    
     
     
         8 . The apparatus of  claim 7 , wherein the contact comprises a third bump including tin and silver.  
     
     
         9 . An apparatus comprising: 
 a substrate including a bond pad;    a passivation layer on the substrate, wherein the passivation layer exposes at least a portion of the bond pad;    a barrier metal on the bond pad;    a bump on the barrier metal; and    a second passivation layer on the passivation layer and adjacent to the bump, wherein the second passivation layer exposes a portion of the bump.    
     
     
         10 . The apparatus of  claim 9 , wherein the substrate includes a device region and a metallization region, the metallization region including a low-k interlayer dielectric material.  
     
     
         11 . The apparatus of  claim 9 , wherein the second passivation layer comprises a spark passivation layer.  
     
     
         12 . The apparatus of  claim 9 , wherein the height of the bump extends beyond the height of the second passivation layer.  
     
     
         13 . A method comprising: 
 forming a bump on a surface of a substrate;    forming a conformal coating over the bump and the surface; and    removing a portion of the conformal coating to expose a portion of the bump and to form a sidewall structure adjacent to the bump and on the surface.    
     
     
         14 . The method of  claim 13 , wherein removing the portion of the conformal coating comprises an anisotropic etch.  
     
     
         15 . The method of  claim 13 , further comprising: 
 flip-chip mounting the substrate to a second substrate having a second bump.    
     
     
         16 . The method of  claim 13 , wherein the sidewall structure has a width in the range of about 1 to 15 microns.  
     
     
         17 . The method of  claim 13 , wherein removing the portion of the conformal coating exposes a portion of the surface.  
     
     
         18 . A method comprising: 
 forming a passivation layer over a substrate including a bond pad;    removing a portion of the passivation layer to expose at least a portion of the bond pad;    forming a barrier metal over the bond pad;    forming a layer over the passivation layer and the barrier metal;    removing a portion of the layer to expose at least a portion of the barrier metal; and    forming a bump over the barrier metal.    
     
     
         19 . The method of  claim 18 , wherein forming the bump comprises electroplating.  
     
     
         20 . The method of  claim 18 , wherein removing the portion of the passivation layer comprises a lithography step and an etch step.  
     
     
         21 . The method of  claim 18 , further comprising: 
 attaching the substrate to a second substrate including a contact, wherein the bump and the contact are electrically connected.    
     
     
         22 . A method for reducing crack propagation from barrier metallization layer undercut in a bumped substrate comprising: 
 securing a fixture to a plurality of bumps on a surface of the bumped substrate;    forming a material between the surface and the fixture;    removing the fixture;    attaching the substrate to a second substrate having a plurality of contacts, wherein at least one bump and at least one contact are electrically connected.    
     
     
         23 . The method of  claim 22 , wherein the material comprises an epoxy.  
     
     
         24 . The method of  claim 22 , wherein the material comprises an underfill material.  
     
     
         25 . The method of  claim 24 , further comprising: 
 curing the underfill material.