Semiconductor integrated circuit and testing method for the same

Abstract

A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

1 - 17 . (canceled)  
   
   
       18 . A method of testing a semiconductor integrated circuit provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving an output command signal from the outside, and 
 an internal circuit having a test input data generation portion, a test end control portion, a test results analysis portion, and a tested circuit portion, and which is controlled by an output clock signal that is output from the clock control portion,    wherein the test input data generation portion, the test end control portion, and the test results analysis portion of the internal circuit use the output clock signal to test the tested circuit portion, the method of testing a semiconductor integrated circuit comprising:    a step (a) of establishing a number of pulses of the output clock signal output by the clock control portion to the internal circuit from a time when the output command signal is received,    a step (b) in which the clock control portion outputs the output clock signal to the internal circuit when a certain time period has passed from said time when the output command signal is received, and    a step (c) of reading out test results from the test results analysis portion after the input of the output clock signal with the number of pulses established in step (a) is complete.    
   
   
       19 . A method of testing a semiconductor integrated circuit provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving an output command signal from the outside, and 
 an internal circuit having a test input data generation portion, a test end control portion having an end signal output portion, a test results analysis portion, and a tested circuit portion, and which is controlled by an output clock signal that is output from the clock control portion,    wherein the test input data generation portion, the test end control portion, and the test results analysis portion of the internal circuit test the tested circuit portion using the output clock signal, the method of testing a semiconductor integrated circuit comprising:    a step (a) of establishing a number of pulses of the output clock signal output to the internal circuit by the clock control portion from a time when the output command signal is received,    a step (b) in which the clock control portion outputs the output clock signal to the internal circuit when a certain time period has passed from the time when the output command signal is received,    a step (c) in which the test end control portion outputs an end signal for ending the test to the end signal output portion when input of the output clock signal with the number of pulses established in step (a) is complete, and    a step (d) of reading out test results from the test results analysis portion, which has received the end signal.    
   
   
       20 . A method of testing a semiconductor integrated circuit provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving an output command signal from the outside, and 
 an internal circuit having a test input data generation portion, a test end control portion, a test results analysis portion, and a tested circuit portion, and which is controlled by an output clock signal that is output from the clock control portion,    wherein the test input data generation portion, the test end control portion, and the test results analysis portion of the internal circuit test the tested circuit portion using the output clock signal, the method of testing a semiconductor integrated circuit comprising:    a step (a) in which the clock control portion outputs the output clock signal to the internal circuit when a certain period of time has passed from a time when the output command signal is received, and    a step (b) of reading out results input to the test results analysis portion,    wherein step (a) and step (b) are repeated.    
   
   
       21 . A method of testing a semiconductor integrated circuit provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving an output command signal from the outside, and 
 an internal circuit having a test input data generation portion, a test end control portion that is provided with a register having a numerical value input portion and with a stop signal output portion, a test results analysis portion, and a tested circuit portion, and which is controlled by an output clock signal that is output from the clock control portion,    wherein the test input data generation portion, the test end control portion, and the test results analysis portion of the internal circuit test the tested circuit portion using the output clock signal, the method of testing a semiconductor integrated circuit comprising:    a step (a) in which the clock control portion inputs, to the numerical value input portion, a number of pulses of the output clock signal that is output to the internal circuit from a time when the output command signal is received,    a step (b) in which the clock control portion outputs the output clock signal to the internal circuit when a certain time period has passed from the time when the output command signal is received,    a step (c) of outputting, to the stop signal output portion, a stop signal for stopping output of the output clock signal to the internal circuit when the number of pulses of the clock signal that is output from the clock control portion matches a numerical value of the numerical value input portion, and    a step (d) of reading out test results from the test results analysis portion,    wherein steps (a) to (d) are repeated with the next step (a) executed simultaneously with step (d).    
   
   
       22 . A method of testing a semiconductor integrated circuit provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving an output command signal from the outside, and 
 an internal circuit having a test input data generation portion, a test end control portion, a test results analysis portion, and a tested circuit portion, and which is controlled by an output clock signal that is output from the clock control portion,    wherein the test input data generation portion, the test end control portion, and the test results analysis portion of the internal circuit test the tested circuit portion using the output clock signal, the method of testing a semiconductor integrated circuit comprising:    a step (a) in which the clock control portion outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received,    a step (b) of reading out results input to the test results analysis portion through step (a), and    a step (c) of repeating step (a) and step (b) and ending the test of the semiconductor integrated circuit at a point where a fault is confirmed in the results that are read out in step (b).    
   
   
       23 . A method of testing a semiconductor integrated circuit provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving an output command signal from the outside, and 
 an internal circuit having a test input data generation portion, a test end control portion that is provided with an end signal output portion, a test results analysis portion, and a. tested circuit portion, and which is controlled by an output clock signal that is output from the clock control portion,    wherein the test input data generation portion, the test end control portion, and the test results analysis portion of the internal circuit test the tested circuit portion using the output clock signal, the method of testing a semiconductor integrated circuit comprising:    a step (a) in which the clock control portion outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received,    a step (b) of reading out results input to the test results analysis portion, and    a step (c) of repeating step (a) and step (b), and when a number of the repetitions has reached a certain number, of performing a fault diagnosis based on the results read out in step (b) after the test end control portion has output an end signal to the end signal output portion.