Method for manufacturing stacked package structure

Abstract

A method for manufacturing a stacked package structure is disclosed, comprising: forming a first chip package structure, comprising: providing a chip carrier having a first and a second surface in opposition to each other; forming bonding wires on the first surface; providing at least one chip on and electrically connected to the first surface; and forming an encapsulant covering the first surface, the chip and the bonding wires, wherein a top end of each bonding wire is exposed at a surface of the encapsulant; forming a plurality of electrical connections respectively deposed on the top end of each bonding wire; and providing a second chip structure electrically jointed with the electrical connections and stacked on the first chip package structure.

1 . A method for manufacturing a stacked package structure, comprising: 
 forming a first chip package structure, comprising:    providing a first chip carrier having a first surface and a second surface in opposition to each other;    forming a plurality of bonding wires on the first surface of the first chip carrier;    providing at least one first chip on and electrically connected to the first surface of the first chip carrier, wherein each bonding wire is higher than the at least one first chip in altitude; and    forming an encapsulant covering the first surface of the first chip carrier, the at least one first chip and the bonding wires, wherein at least one top end of each bonding wire is exposed at a surface of the encapsulant; and    providing a second chip package structure electrically connected to and stacked on the first chip package structure.    
   
   
       2 . The method for manufacturing a stacked package structure according to  claim 1 , wherein before providing the second chip package structure, forming a plurality of first electrical connections respectively deposed on the top end of each bonding wire, so that the second chip package structure is electrically connected to the first chip package structure via the first electrical connections.  
   
   
       3 . The method for manufacturing a stacked package structure according to  claim 1 , wherein the step of forming the encapsulant comprises: 
 providing an encapsulant material layer to cover the first surface of the first chip carrier, the at least one first chip and the bonding wires; and    performing a grinding step to remove a portion of the encapsulant material layer, until the top end of each bonding wire is exposed.    
   
   
       4 . The method for manufacturing a stacked package structure according to  claim 3 , wherein the grinding step is a mechanical grinding step or a chemical grinding step.  
   
   
       5 . The method for manufacturing a stacked package structure according to  claim 2 , wherein the step of forming the first chip package structure further comprises forming a plurality of second electrical connections respectively deposed on the second surface of the first chip carrier.  
   
   
       6 . The method for manufacturing a stacked package structure according to  claim 1 , wherein a material of the bonding wires is selected from the group consisting of Cu, Al, Au, Sn and an alloy thereof.  
   
   
       7 . The method for manufacturing a stacked package structure according to  claim 2 , wherein the step of forming the first electrical connections is performed by a direct ball attach method, a screen print method, an electro plating method or an electroless plating method.  
   
   
       8 . The method for manufacturing a stacked package structure according to  claim 1 , wherein before the step of forming the encapsulant, the step of forming the first chip package structure further comprises forming at least one passive device on the first surface of the first chip carrier.  
   
   
       9 . The method for manufacturing a stacked package structure according to  claim 1 , wherein the step of providing the second chip structure comprises: 
 providing a second chip carrier having a first surface and a second surface in opposition to each other;    forming a plurality of electrical connection devices on the first surface of the second chip carrier;    providing at least one second chip on and electrically connected to the first surface of the second chip carrier, wherein each electrical connection device is higher than the at least one second chip in altitude; and    forming another encapsulant covering the first surface of the second chip carrier, the at least one second chip and the electrical connection devices, wherein a top end of each electrical connection device is exposed at a surface of the another encapsulant.    
   
   
       10 . The method for manufacturing a stacked package structure according to  claim 9 , wherein the step of forming the another encapsulant comprises: 
 providing an encapsulant material layer to cover the first surface of the second chip carrier, the at least one second chip and the electrical connection devices; and    performing a grinding step to remove a portion of the encapsulant material layer, until the top end of each electrical connection device is exposed.    
   
   
       11 . The method for manufacturing a stacked package structure according to  claim 9 , wherein the electrical connection devices are selected from the group consisting of bonding wires, conductive studs, pins, electronic components and any combination thereof.  
   
   
       12 . The method for manufacturing a stacked package structure according to  claim 1 , wherein the chip carrier is a substrate or a leadframe.  
   
   
       13 . The method for manufacturing a stacked package structure according to  claim 2 , wherein the first electrical connections are connection bumps or balls.