Method for making semiconductor transistor

Abstract

A semiconductor transistor includes a substrate, a gate insulating layer positioned on the surface of the substrate, a gate positioned on the gate insulating layer, a channel region positioned in the substrate corresponding to the gate, and a source region and a drain region respectively positioned alongside the channel region. The source region and the drain region are mainly made of a first material and a second material, wherein the first material and the second material have a same lattice structure and different spacing. The source region and the drain region each include a main region in which a percentage of the second material is constant, and a peripheral region in which a percentage of the second material is graded.

1 . A method for forming a semiconductor transistor comprising: 
 providing a substrate, the substrate comprising a gate insulating layer positioned on the surface of the substrate, a gate positioned on the gate insulating layer, and a channel region positioned in the substrate corresponding to the gate;    forming two recesses in the substrate alongside the channel region;    forming a first material and a second material in the recesses to respectively form two peripheral regions, the first material and the second material having a same lattice structure and different spacing, and a percentage of the second material in the peripheral regions being graded; and    forming the first material and the second material in the recesses to respectively form two main regions above the peripheral regions, and a percentage of the second material in the main regions being constant.    
   
   
       2 . The method of  claim 1 , wherein the percentage of the second material in each peripheral region decreases from an interface between the main region and the peripheral region to an interface between the peripheral region and the substrate.  
   
   
       3 . The method of  claim 2 , wherein the percentage of the second material in each peripheral region decreases from 30% to 0%.  
   
   
       4 . The method of  claim 3 , wherein the percentage of the second material in each main region is approximately 30%.  
   
   
       5 . The method of  claim 1 , wherein the first material is monocrystalline silicon.  
   
   
       6 . The method of  claim 1 , wherein the second material is germanium.  
   
   
       7 . The method of  claim 6 , wherein the semiconductor transistor is P type.  
   
   
       8 . The method of  claim 1 , wherein the second material is carbon.  
   
   
       9 . The method of  claim 8 , wherein the semiconductor transistor is N type.  
   
   
       10 . The method of  claim 1 , wherein the first material and the second material are epitaxially grown in the recesses.  
   
   
       11 . The method of  claim 1 , further comprising forming two lightly doped regions positioned in the substrate respectively alongside the channel region prior to forming the recesses.  
   
   
       12 . The method of  claim 1 , further comprising performing an implantation process to form a source region and a drain region subsequent to forming the main regions.