Integrated passive devices

Abstract

The specification describes an integrated passive device (IPD) that is formed on a polysilicon substrate. A method for making the IPD is disclosed wherein the polysilicon substrate is produced starting with a single crystal handle wafer, depositing a thick substrate layer of polysilicon on one or both sides of the starting wafer, forming the IPD on one of the polysilicon substrate layers, and removing the handle wafer. In a preferred embodiment the single crystal silicon handle wafer is a silicon wafer rejected from a single crystal silicon wafer production line.

1 . An integrated passive device (IPD) comprising: 
 a polysilicon wafer substrate, the polysilicon wafer substrate having a resistivity of more than 0.1 Kohm-cm,    a plurality of thin film passive devices on the polysilicon wafer substrate, and    electrical interconnections interconnecting the thin film passive devices.    
     
     
         2 . The device of  claim 1  wherein the polysilicon wafer substrate has a thickness greater than 200 microns.  
     
     
         3 . The device of  claim 1  wherein the IPD comprises a plurality of inductors, and a plurality of passive resistor and/or capacitor devices.  
     
     
         4 . The device of  claim 3  wherein the plurality of inductors are physically grouped together on a first portion of the polysilicon substrate, and the plurality of passive resistor and/or capacitor devices are grouped together on a second portion of the polysilicon substrate.  
     
     
         5 . The device of  claim 1  further including an active IC chip mounted on the IPD.  
     
     
         6 . The device of  claim 4  further including an active IC chip mounted on the second portion of the polysilicon substrate.  
     
     
         7 . The device of  claim 1  wherein the polysilicon wafer substrate comprises a polysilicon substrate layer on a single crystal silicon wafer.  
     
     
         8 . The device of  claim 1  wherein the polysilicon wafer substrate comprises two polysilicon layers with a single crystal silicon wafer between the two polysilicon layers.  
     
     
         9 . The device of  claim 7  wherein the polysilicon substrate layer is deposited on the single crystal silicon wafer.  
     
     
         10 . The device of  claim 7  wherein the single crystal silicon wafer is a refuse wafer.  
     
     
         11 . The device of  claim 7  wherein the single crystal silicon wafer has a diameter of at least 8 inches.  
     
     
         12 . A substrate comprising a planar single crystal silicon wafer and a planar layer of polysilicon on one side of the wafer.  
     
     
         13 . The substrate of  claim 12  wherein the layer of polysilicon has a resistivity of more than 0.1 Kohm-cm,  
     
     
         14 . A substrate comprising a planar single crystal silicon wafer, a planar layer of polysilicon on one side of the wafer, and a planar layer of polysilicon on the other side of the wafer.