Digital clock recovery circuit

Abstract

A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.

1 . A clock circuit, comprising: 
 circuitry to provide a first indication indicating whether an edge in an input signal lags or precedes a clock edge in a clock signal;    a frequency estimator that estimates a frequency difference between the input signal and the clock signal to provide a second indication indicating the magnitude of the frequency difference; and    a phase adjuster to adjust the phase of the clock signal based on the first indication and the second indication.    
   
   
       2 . The clock circuit of  claim 1 , wherein the phase adjuster comprises: 
 a phase controller that provides a phase setting signal based on the first and second indications; and    a phase interpolator to adjust the phase of the clock signal responsive to the phase setting signal.    
   
   
       3 . The clock circuit of  claim 1 , further comprising a first filter coupled between the circuitry and the frequency estimator to filter the first indication before it is received by the frequency estimator, wherein the frequency estimator comprises: 
 a second filter to further filter the first indication;    a frequency counter that, responsive to the further filtered first indication, produces an output that represents an estimated difference in frequency between the clock signal and the input signal; and    a frequency synthesizer to produce the second indication responsive to the estimated frequency difference.    
   
   
       4 . The clock circuit of  claim 3 , wherein the frequency synthesizer comprises: 
 a divide-by-X counter to divide the clock by a number X that is based on the estimated frequency difference, the divided clock providing the second indication to the phase controller.    
   
   
       5 . The clock circuit of  claim 4 , further comprising: 
 a converter to convert the estimated frequency difference to a corresponding period, the number X being responsive to the period.    
   
   
       6 . The clock circuit of  claim 5 , wherein the divide-by-X counter comprises: 
 a divide-by-K counter, where K is a fixed number; and    a divide-by-V counter, where V is responsive to the period.    
   
   
       7 . The clock circuit of  claim 6 , wherein the divide-by-K counter is common to plural clock recovery circuits.  
   
   
       8 . The clock circuit of  claim 5 , wherein the converter comprises a read-only-memory (ROM) containing a conversion table.  
   
   
       9 . The clock circuit of  claim 5 , wherein the converter performs a 1's complement of a magnitude portion of the estimated frequency difference.  
   
   
       10 . The clock circuit of  claim 5 , wherein the converter is implemented with a microprocessor.  
   
   
       11 . The clock circuit of  claim 10 , wherein at least a portion of the divide-by-X counter is implemented with a microprocessor.  
   
   
       12 . The clock circuit of  claim 4 , wherein the frequency counter is a saturating counter.  
   
   
       13 . The clock circuit of  claim 1 , wherein the second indication includes a pulse stream having a frequency proportional to the frequency difference.  
   
   
       14 . The clock circuit of  claim 1 , wherein the phase controller includes a phase counter, the phase counter being configured to increment according to the first indication and further increment at a steady rate corresponding to the frequency difference indicated by the second indication.  
   
   
       15 . The clock circuit of  claim 1 , wherein the phase controller includes at least one first input to receive the first indication and at least one second input to receive the second indication.  
   
   
       16 . The clock circuit of  claim 1 , further comprising a filter coupled between the circuitry and the phase controller to filter the first indication before it is received by the phase controller.  
   
   
       17 . The clock circuit of  claim 1 , wherein the frequency estimator that estimates the frequency difference based on the first indication.  
   
   
       18 . The clock circuit of  claim 1 , wherein the phase adjuster rotates the phase of the clock signal based on the second indication  
   
   
       19 . A method of providing a clock, comprising: 
 generating a first indication indicating whether an edge of an input signal lags or leads a clock edge of a clock signal;    producing a second indication indicating a frequency difference between the input signal and the clock signal; and    adjusting the phase of the clock signal based on the first indication and the second indication.    
   
   
       20 . The method of  claim 19 , wherein the producing comprises: 
 dividing the clock signal by a number X which is based on the estimated frequency difference, the adjusting being responsive to the divided clock.    
   
   
       21 . The method of  claim 20 , further comprising: 
 converting the estimated frequency difference to a corresponding period, the number X being responsive to the period.    
   
   
       22 . The method of  claim 21 , dividing the clock by X comprises: 
 dividing the clock signal by a number K, where K is a fixed number; and    dividing the clock signal by a number V, where V is responsive to the period.    
   
   
       23 . The method of  claim 22 , wherein the divide-by-K counter is common to plural clock circuits.  
   
   
       24 . The method of  claim 21 , wherein the converting includes using a stored conversion table to convert.  
   
   
       25 . The method of  claim 21 , wherein the converting includes using a 1's complement of a magnitude portion of the estimated frequency difference.  
   
   
       26 . The method of  claim 21 , wherein the converting is performed by a microprocessor.  
   
   
       27 . The method of  claim 24 , wherein dividing by X is performed at least partially in a microprocessor.  
   
   
       28 . The method of  claim 20 , wherein the producing a signal is performed with a saturating counter.  
   
   
       29 . The method of  claim 19 , wherein the second indication includes a pulse stream having a frequency proportional to the frequency difference.  
   
   
       30 . The method of  claim 19 , wherein the producing the second indication is based on the first indication.  
   
   
       31 . The method of  claim 19 , wherein adjusting the phase of the clock signal includes rotating the phase based on the second indication.  
   
   
       32 . A clock system, comprising: 
 logic means for providing first indication indicating whether an edge of an input signal lags or leads a clock edge of a clock signal;    frequency estimator means for estimating a frequency difference between the input signal and the clock signal, and for producing a second indication indicating the frequency difference; and    phase controller means for adjusting the phase of the clock signal based on the first indication and rotating the phase based on the second indication.    
   
   
       33 . A method of generating a pulse stream, comprising: 
 providing a first indication indicating whether an edge of an input signal lags or precedes a clock edge in a clock signal;    based on the first indication, estimating a frequency difference between the input signal and the clock signal; and    producing a pulse stream having a frequency based on the frequency difference.    
   
   
       34 . The method of  claim 33 , wherein the producing comprises: 
 dividing the clock signal by a number X which is based on the estimated frequency difference, the producing being responsive to the divided clock.    
   
   
       35 . The method of  claim 34 , further comprising: 
 converting the estimated frequency difference to a corresponding period, the number X being responsive to the period.    
   
   
       36 . The method of  claim 35 , wherein dividing the clock by X comprises: 
 dividing the clock signal by a number K, where K is a fixed number; and    dividing the clock signal by a number V, where V is responsive to the period.    
   
   
       37 . The method of  claim 36 , wherein the divide-by-K counter is common to plural clock circuits.  
   
   
       38 . The method of  claim 35 , wherein the converting includes using a stored conversion table to convert.  
   
   
       39 . The method of  claim 35 , wherein the converting includes using a 1's complement of a magnitude portion of the estimated frequency difference.  
   
   
       40 . The method of  claim 35 , wherein the converting is performed by a microprocessor.  
   
   
       41 . The method of  claim 40 , wherein dividing by X is performed at least partially in a microprocessor.  
   
   
       42 . The method of  claim 33 , wherein the pulse stream indicates magnitude of the frequency difference.  
   
   
       43 . A pulse stream generator circuit, comprising: 
 a frequency counter to receive a first indication indicating whether an edge of an input signal lags or precedes a clock edge in a clock signal, the frequency counter generating a value corresponding to a frequency difference between the input signal and the clock signal; and    a frequency synthesizer that, based on the value, generates a pulse stream having a frequency based on the value.    
   
   
       44 . The generator circuit of  claim 43 , wherein the value includes a sign-magnitude value including a magnitude component indicating degree of the frequency difference and a sign component indicating direction of the frequency difference.  
   
   
       45 . The generator circuit of  claim 44 , wherein the frequency synthesizer includes a read-only memory (ROM) that determines a frequency of the pulse stream based on the magnitude component.  
   
   
       46 . The generator circuit of  claim 45 , wherein the frequency synthesizer includes a divider circuit that divides a received reference clock based on the frequency determined by the ROM.  
   
   
       47 . The generator circuit of  claim 44 , wherein the frequency synthesizer includes a logic circuit that, as a function of the magnitude component, generates the pulse stream by enabling and disabling at least one gate receiving a reference clock.  
   
   
       48 . The generator circuit of  claim 44 , wherein the frequency synthesizer includes a central processing unit (CPU) that determines a frequency of the pulse stream based on the magnitude component.  
   
   
       49 . The generator circuit of  claim 43 , further comprising a filter to filter the first indication.  
   
   
       50 . The generator circuit of  claim 43 , wherein the pulse stream indicates magnitude of the frequency difference.  
   
   
       51 . The generator circuit of  claim 43 , wherein the pulse stream has a frequency proportional to the frequency difference.