System to detect and identify errors in control information, read data and/or write data

Abstract

An integrated circuit, such as an integrated circuit memory or buffer device, method and system, among other embodiments, generate a plurality of error codes, such as CRC codes, corresponding to control information, write data and read data transactions, respectively. The plurality of separately generated CRC codes is logged or stored in respective storage circuits, such as circular buffers. The stored plurality of CRC codes corresponding to each transaction then may be used to determine whether an error occurred during a particular transaction and thus whether a retry of the particular transaction is issued. The integrated circuit includes a compare circuit to compare a CRC code generated by the integrated circuit with a CRC code provided by a controller device. A CRC code corresponding to read data is transferred to a controller device using a data mask signal line that is not being used during a read transaction. The CRC code generated by the integrated circuit then may be compared to a CRC code generated by the controller device to determine whether an error occurred. The controller device generates and stores a plurality of CRC codes, corresponding to control information, write data and read data. The controller device then compares the CRC codes generated by the controller device with CRC codes generated and stored in the integrated circuit to determine whether an error has occurred during a particular transaction.

1 . An integrated circuit device comprising:
 a first storage circuit to store a first code that represents write data to be stored in a storage array;   a second storage circuit to store a second code that represents read data obtained from the storage array; and   a third storage circuit to store a third code that represents control information used to access the storage array.   
   
   
       2 . The integrated circuit device of  claim 1 , wherein the integrated circuit device is a buffer device to transfer write data from a controller device to an integrated circuit memory device including the storage array and to transfer read data from the integrated circuit memory device to the controller device. 
   
   
       3 . The integrated circuit device of  claim 1 , wherein the integrated circuit is an integrated circuit memory device including the storage array to store the write data. 
   
   
       4 . The integrated circuit device of  claim 1 , wherein the control information includes address information for accessing a row of the storage array and a memory command. 
   
   
       5 . The integrated circuit device of  claim 1  further comprising:
 a first encode circuit to provide the first code in response to the write data;   a second encode circuit to provide the second code in response to the read data; and   a third encode circuit to provide the third code in response to the control information.   
   
   
       6 . The integrated circuit device of  claim 1  further comprising:
 a compression circuit to provide a first compressed code in response to the third code; and   a comparison circuit to compare the first compressed code with a code that is received to determine whether an error has occurred.   
   
   
       7 . The integrated circuit device of  claim 1 , wherein the first, second and third storage circuits include first, second and third circular buffers to store a first plurality of codes representing write data, a second plurality of codes representing read data, and a third plurality of codes representing control information. 
   
   
       8 . The integrated circuit of  claim 1 , wherein the first, second and third codes are cycle redundancy checking codes. 
   
   
       9 . A method for operation of an integrated circuit device, the method comprising:
 generating a first code that represents write data to be stored in a storage array;   storing the first code;   generating a second code that represents read data obtained from the storage array;   storing the second code;   generating a third code that represents control information used to access the storage array; and   storing the third code.   
   
   
       10 . The method of  claim 9 , further comprising:
 receiving a fourth code from a controller device;   comparing the fourth code with the third code to generate an error signal; and   retrying a memory transaction in response to the error signal.   
   
   
       11 . The method of  claim 10 , wherein the fourth code is received from a signal line used to transfer mask information. 
   
   
       12 . The method of  claim 10 , wherein the control information includes an address for accessing a row of the storage array. 
   
   
       13 . The method of  claim 9 , further comprising:
 transferring the first code to a controller device that compares the first code with a fourth code to generate an error signal indicating an occurrence of erroneous write data;   transferring the second code to a controller device that compares the second code with a fifth code to generate an error signal indicating an occurrence of erroneous read data;   transferring the third code to a controller device that compares the third code with a sixth code to generate an error signal indicating an occurrence of erroneous control information.   
   
   
       14 . The method of  claim 13 , further comprising:
 retrying transferring the write data in response to the error signal indicating an occurrence of erroneous write data;   retrying transferring the read data in response to the error signal indicating an occurrence of erroneous read data; and   retrying transferring control information in response to the error signal indicating an occurrence of erroneous control information.   
   
   
       15 . The method of  claim 9 , wherein the integrated circuit device is a buffer device to transfer write data from a controller device to an integrated circuit memory device including the storage array and to transfer read data from the integrated circuit memory device to the controller device. 
   
   
       16 . The method of  claim 9 , wherein the first, second and third codes are cycle redundancy checking codes. 
   
   
       17 . A method for operation of an integrated circuit memory device, the method comprising:
 generating a code indicating an error occurred in an access of the integrated circuit memory device;   determining a type of error that occurred in an access of the integrated circuit memory device; and   retrying an access of the integrated circuit memory device in response to the type of error.   
   
   
       18 . The method of  claim 17 , wherein the access of the integrated circuit memory device includes providing control information to the integrated circuit memory device, the control information including an address to a storage array of the integrated circuit memory device. 
   
   
       19 . The method of  claim 17 , wherein the access of the integrated circuit memory device includes providing write data to be stored in a storage array of the integrated circuit memory device. 
   
   
       20 . The method of  claim 17 , wherein the access of the integrated circuit memory device includes providing read data from a storage array of the integrated circuit memory device. 
   
   
       21 . The method of  claim 17 , wherein generating the code includes compressing the code. 
   
   
       22 . The method of  claim 17 , wherein the determining includes reading a code representing control information from a first storage circuit disposed on the integrated circuit memory device having a storage array, reading a code representing a write data from a second storage circuit disposed on the integrated circuit memory device and reading a code representing read data from a third storage circuit disposed on the integrated circuit memory device. 
   
   
       23 . The method of  claim 17 , wherein a type of error is selected from one of an error in the control information transferred to the integrated circuit memory device, an error in the write data to be stored in a storage array of the integrated circuit memory device and an error in the read data obtained from the storage array of the integrated circuit memory device. 
   
   
       24 . A system, comprising:
 a controller including,
 a first storage circuit to store a first code that represents write data to be stored in a storage array; 
 a second storage circuit to store a second code that represents read data obtained from the storage array; 
 a third storage circuit to store a third code that represents control information used to access the storage array; and 
   an integrated circuit including,
 a fourth storage circuit to store a fourth code that represents write data to be stored in a storage array; 
 a fifth storage circuit to store a fifth code that represents read data obtained from the storage array; 
 a sixth storage circuit to store a sixth code that represents control information used to access the storage array. 
   
   
   
       25 . The system of  claim 24 , wherein the controller device includes a compare circuit to compare the third code with the sixth code to determine when to retry a memory command. 
   
   
       26 . The system of  claim 25 , wherein the compare circuit compares the first code with the fourth code to determine when to retransfer the write data from the controller device to the integrated circuit. 
   
   
       27 . The system of  claim 25 , wherein the compare circuit compares the second code with the fifth code to determine when to retransfer the read data from the integrated circuit to the controller device. 
   
   
       28 . The system of  claim 24 , wherein the controller device and the integrated circuit is coupled by a serial interconnect, wherein the third, fourth and fifth codes are transferred to the controller device on the serial interconnect. 
   
   
       29 . The system of  claim 24 , wherein the first, second, third, fourth and fifth codes are cycle redundancy checking codes. 
   
   
       30 . Machine-readable media including information that represents an apparatus, the represented apparatus comprising:
 a first storage circuit to store a first code that represents write data to be stored in a storage array;   a second storage circuit to store a second code that represents read data obtained from the storage array; and   a third storage circuit to store a third code that represents control information used to access the storage array.   
   
   
       31 . An integrated circuit comprising:
 an interface to transfer write data, read data and control information; and   means for encoding the write data, read data and control information into an error code representing write data, read data, and control information and,   the means for encoding including determining whether an error occurred in transferring one of the write data, read data and control information in response to the error code.