Method of fabricating semiconductor device

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

1 .- 21 . (canceled)  
   
   
       22 . A semiconductor device having a MISFET forming region and a gate lead-out region formed on a main surface of a semiconductor substrate, comprising: 
 a trench formed in the semiconductor substrate at the MISFET forming region;    a gate insulating film of a MISFET formed in the trench;    a gate electrode of the MISFET formed on the gate insulating film and in the trench,    the MISFET forming region being divided into plural island regions by the trench,    the plural island regions being spaced from each other by the trench and arranged in a matrix;    a first conductive film formed over the semiconductor substrate in the gate lead-out region and integrally formed with the gate electrode,    wherein the top surface of the gate electrode is lower than the top surface of the semiconductor substrate in the gate lead-out region;    a source region of the MISFET formed in the semiconductor substrate; and    a drain region of the MISFET formed in the semiconductor and formed under the source region such that a channel forming region is arranged, in a depth direction of the semiconductor substrate, between the source region and the drain region.    
   
   
       23 . A semiconductor device according to  claim 22 , 
 wherein the MISFET forming region is located on only one side of the gate lead-out region.    
   
   
       24 . A semiconductor device according to  claim 22 , 
 wherein the first conductive film and the gate electrode are comprised of a silicon film.    
   
   
       25 . A semiconductor device having a MISFET forming region and a gate lead-out region formed on a main surface of a semiconductor substrate, comprising: 
 a trench formed in the semiconductor substrate at the MISFET forming region;    a gate insulating film of a MISFET formed in the trench,    a gate electrode of the MISFET formed on the gate insulating film and in the trench,    the MISFET forming region being divided into plural island regions by the trench, p 1  the plural island regions being spaced from each other by the first trench and arranged in a matrix; and    a first conductive film formed over the semiconductor substrate in the gate lead-out region and integrally formed with the gate electrode,    wherein the top surface of the gate electrode is lower than the top surface of the semiconductor substrate in the gate lead-out region.    
   
   
       26 . A semiconductor device according to  claim 25 , 
 wherein the MISFET forming region is located on only one side of the gate lead-out region.    
   
   
       27 . A semiconductor device according to  claim 25 , 
 wherein first conductive film and the gate electrode are comprised of a silicon film.    
   
   
       28 . A metal insulator semiconductor field effect type semiconductor device comprising: 
 a semiconductor body having a first major surface and a second major surface which are opposite to each other,    the first major surface including an element forming region for a metal insulator semiconductor field effect type element and a peripheral region for a gate lead-out electrode of the element;    a trench formed in the element forming region from the first major surface into the semiconductor body excluding the peripheral region, so that the element forming region is divided into plural island regions by the trench,    the plural island regions being spaced from each other by the trench and being arranged in a matrix,    outermost ones of the plural island regions, which are located in the outermost row or column of the matrix, being spaced from the peripheral region by the trench,    a first insulation film formed over a side surface and a bottom of the trench and over the peripheral region of the first major surface;    an electrode conductive film disposed over the first insulation film and in the trench so as to be extended from the trench onto the peripheral region of the first major surface,    a first part of the electrode conductive film being disposed in the trench and serving as a gate electrode for each of the island regions,    a second part of the electrode conductive film being disposed over the peripheral region and being contiguous with the first part,    the second part of the electrode conductive film serving as a gate lead-out electrode electrically connected to the gate electrode,    wherein the top surface of the first part is lower than the top surface of the semiconductor substrate in the peripheral region.    
   
   
       29 . A semiconductor device according to  claim 28 , 
 wherein the electrode conductive film is comprised of a silicon film.    
   
   
       30 . A semiconductor device having a MISFET forming region and a gate lead-out region formed on a main surface of a semiconductor substrate, comprising: 
 a trench formed in the semiconductor substrate at the MISFET forming region;    a gate insulating film of a MISFET formed in the first trench;    a gate electrode of the MISFET formed on the gate insulating film and in the trench,    the MISFET forming region being divided into plural island regions by the trench,    the plural island regions spaced from each other by the trench;    a first conductive film formed over the semiconductor substrate in the gate lead-out region and integrally formed with the gate electrode,    wherein the top surface of the gate electrode is lower than the top surface of the semiconductor substrate in the gate lead-out region;    a source region of the MISFET formed in the semiconductor substrate; and    a drain region of the MISFET formed in the semiconductor substrate and formed under the source region such that a channel forming region is arranged, in a depth direction of the semiconductor substrate, between the source region and the drain region.    
   
   
       31 . A semiconductor device according to  claim 30 , 
 wherein the MISFET forming region is located on only one side of the gate lead-out region.    
   
   
       32 . A semiconductor device according to  claim 30 , 
 wherein the first conductive film and the gate electrode are comprised of a silicon film.    
   
   
       33 . A semiconductor device having a MISFET forming region and a gate lead-out region formed on a main surface of a semiconductor substrate, comprising: 
 a trench formed in the semiconductor substrate at the MISFET forming region;    a gate insulating film of a MISFET formed in the trench;    a gate electrode of the MISFET formed on the gate insulating film and in the trench,    the MISFET forming region being divided into plural island regions by the trench,    the plural island regions being spaced from each other by the trench; and    a first conductive film formed over the semiconductor substrate in the gate lead-out region and integrally formed with the gate electrode,    wherein the top surface of the gate electrode is lower than the top surface of the semiconductor substrate in the gate lead-out region.    
   
   
       34 . A semiconductor device according to  claim 33 , 
 wherein the MISFET forming region is located on only one side of the gate lead-out region.    
   
   
       35 . A semiconductor device according to  claim 33 , 
 wherein the first conductive film and the gate electrode are comprised of a silicon film.    
   
   
       36 . A metal insulator semiconductor field effect type semiconductor device comprising: 
 a semiconductor body having a first major surface and a second major surface which are opposite to each other,    the first major surface including an element forming region for a metal insulator semiconductor field effect type element and a peripheral region for a gate lead-out electrode of the element;    a trench formed in the element forming region from the first major surface into the semiconductor body excluding the peripheral region, so that the element forming region is divided into plural island regions by the trench,    the plural island regions being spaced from each other by the trench,    outermost ones of the plural island regions being spaced from the peripheral region by the trench,    a first insulation film formed over a side surface and a bottom of the trench and over the peripheral region of the first major surface;    an electrode conductive film disposed over the first insulation film and in the trench so as to be extended from the trench onto the peripheral region of the first major surface,    a first part of the electrode conductive film being disposed in the trench and serving as a gate electrode for each of the island regions,    a second part of the electrode conductive film being disposed over the peripheral region and being contiguous with the first part,    the second part of the electrode conductive film serving as a gate lead-out electrode electrically connected to the gate electrode,    wherein the top surface of the first part is lower than the top surface of the semiconductor substrate in the peripheral region.    
   
   
       37 . A semiconductor device according to  claim 36 , 
 wherein the electrode conductive film is comprised of a silicon film.