Thermally Enhanced Three-Dimensional Package and Method for Manufacturing the Same

Abstract

A thermally enhanced three-dimensional (3D) package is disclosed. The package includes a heat sink having an opening and a stiffener ring inside the opening. The stiffener ring has a first surface and a second surface. A first substrate of a first package is disposed inside the opening and secured to the first surface of the stiffener ring. A second substrate of a second chip package is secured to the second surface of the stiffener ring. The first substrate is connected to the second substrate through a plurality of solder balls. The heat generated in the first chip package and the second chip package is dissipated by the heat sink. The first chip package and the second chip package are fixed by the stiffener ring to eliminate warpage of the first chip package and the second chip package, thereby assuring the electrical transmission of the product.

1 . A thermally enhanced three-dimensional package comprising: 
 a heat sink having an opening, and a first surface and a second surface in the opening;    a first chip package having a first substrate, wherein the first substrate is secured to the first surface;    a second chip package having a second substrate, wherein the second substrate is secured to the second surface; and    a plurality of solder balls connected to the first chip package and the second chip package, wherein the first chip package and the second chip package are stacked over each other.    
   
   
       2 . The thermally enhanced three-dimensional package of  claim 1 , wherein the opening of the heat sink comprises a step shape.  
   
   
       3 . The thermally enhanced three-dimensional package of  claim 1 , wherein the first chip package comprises a first chip electrically connected to the first substrate.  
   
   
       4 . The thermally enhanced three-dimensional package of  claim 1  further comprising a plurality of external conductive devices disposed on the first substrate of the first chip package.  
   
   
       5 . The thermally enhanced three-dimensional package of  claim 4 , wherein the external conductive devices are exposed from the opening of the heat sink.  
   
   
       6 . The thermally enhanced three-dimensional package of  claim 1 , wherein the second chip package comprises a second chip electrically connected to the second substrate.