SRAM split write control for a delay element

Abstract

A Static Random Access Memory (SRAM) having a split write control is described. The SRAM includes bit, write, and write-word lines. Each memory cell within the SRAM includes a delay which is coupled to a dedicated write-word line. When a cell is not being written, its delay receives a delay signal on its associated write-word line, which increases the response time of the cell. When a cell is to be written, however, its delay receives a bypass signal on its associated write-word line, which decreases the response time of the SRAM cell.

1 . A method of operating a Static Random Access Memory (SRAM) comprising a plurality of SRAM memory words arranged in a plurality of columns and a plurality of rows, wherein each memory word includes at least one SRAM memory cell that includes a delay coupled with a pair of feedback elements, and wherein each pair of feedback elements is coupled to a pass gate, the method comprising: 
 a. enabling the delay of each memory cell within the SRAM, wherein the delay, in operation, increases the response time of the pair of feedback elements associated with each memory cell in the SRAM; and    b. when a first memory cell located within a first memory word is to be written to: 
 1. disabling the delay of each memory cell within the first memory word;  
 2. enabling the pass gates of the memory cells located in the first row; and  
 3. providing a write voltage to the pass gates of the memory cells located in the first column, thereby communicating the write voltage to the pair of feedback elements of the first memory cell.  
   
     
     
         2 . The method as in  claim 1 , wherein enabling the delay comprises increasing the response time associated with the pair of feedback elements of each memory cell within the SRAM to a value greater than a recovery time associated with a radiation event.  
     
     
         3 . The method as in  claim 2 , wherein the radiation event is a particle strike and the recovery time is a time associated with the dissipation of charge from the particle strike.  
     
     
         4 . The method as in  claim 1 , further comprising: 
 after the first memory cell has been written to, re-enabling the delay of each memory cell within the first memory word.    
     
     
         5 . The method as in  claim 1 , wherein disabling the delay comprises communicating a bypass signal to a dedicated signal line coupled to an input terminal associated with the delay each memory cell within the first memory word.  
     
     
         6 . The method as in  claim 5 , wherein providing the write voltage to the pass gates of the first column comprises communicating the write voltage to a first signal line coupled to an input terminal associated with the pass gate of each memory cell located in the first column.  
     
     
         7 . The method as in  claim 6 , wherein enabling the pass gates of the memory cells located in the first row comprises communicating an enable signal to a second signal line coupled to a gate terminal associated with the pass gate of each memory cell located in the first row.  
     
     
         8 . The method as in  claim 1 , further comprising: 
 when the first memory cell is to be read:    enabling the pass gates of the memory cells located in the first row; and    communicating a stored voltage being stored by the pair of feedback elements of the first memory cell via a first signal line coupled to an input terminal associated with the pass gate of each memory cell located in the first column.    
     
     
         9 . A Static Random Access Memory (SRAM), comprising: 
 first and second bit lines for communicating data signals;    first and second word lines for communicating enable signals;    first, second, third, and fourth SRAM memory cells each including a delay component and an associated pair of feedback elements, the delay, in operation, increasing the response time of its associated pair of feedback elements, the first and second memory cells coupled to the first word line, the third and fourth memory cells coupled to the second word line, the first and third memory cells coupled to the first bit line, and the second and fourth memory cells coupled to the second bit line; and    first, second, third, and fourth write-word lines for communicating delay and bypass signals, the first write-word line coupled to the delay of the first memory cell, the second write-word line coupled to the delay of the second memory cell, the third write-word line coupled to the delay of the third memory cell, and the fourth write-word line coupled to the delay of the fourth memory cell.    
     
     
         10 . The device as in  claim 9 , wherein the enable signals and the data signals are used in combination to read from and write to each memory cell within the SRAM.  
     
     
         11 . The device as in  claim 9 , wherein, each memory cell within the SRAM receives the delay signal on its respective write-word line when it is not being written to, the delay signal increasing a response time of the memory cell it is communicated to.  
     
     
         12 . The device as in  claim 11 , wherein the increased response time is greater than a recovery time associated with a single event upset of the SRAM.  
     
     
         13 . The device as in  claim 12 , wherein each write-word line transmits the bypass signal when its associated memory cell is to be written to, the bypass signal decreasing the response time of the associated memory cell.  
     
     
         14 . The device as in  claim 13 , wherein the decreased response time is less than the recovery time of the first memory cell.  
     
     
         15 . A method of operating a Static Random Access Memory (SRAM), the method comprising: 
 increasing the delay time of each SRAM memory cell within the SRAM with a plurality of dedicated write-word lines, each write-word line communicating delay and bypass signals and being exclusively coupled to one memory word within the SRAM; and    when a selected memory word is to be written, decreasing only the delay time of the memory word via its associated write-word line.    
     
     
         16 . The method as in  claim 15 , wherein the memory word includes at least one memory cell.  
     
     
         17 . The method as in  claim 15 , further comprising: 
 after the selected memory word is written, increasing the delay time of the selected memory word via its associated write-word line.    
     
     
         18 . The method as in  claim 17 , further comprising: 
 when the selected memory word is to be read, maintaining the delay time of the selected memory word via its associated write-word line.