Method of forming high voltage n-ldmos transistors having shallow trench isolation region with drain extensions

Abstract

A method and structure is disclosed for a transistor having a gate, a channel region below the gate, a source region on one side of the channel region, a drain region on an opposite side of the channel region from the source region, a shallow trench isolation (STI) region in the substrate between the drain region and the channel region, and a drain extension below the STI region. The drain extension is positioned along a bottom of the STI region and along a portion of sides of the STI. Portions of the drain extension along the bottom of the STI may comprise different dopant implants than the portions of the drain extensions along the sides of the STI. Portions of the drain extensions along sides of the STI extend from the bottom of the STI to a position partially up the sides of the STI. The STI region is below a portion of the gate. The drain extension provides a conductive path between the drain region and the channel region around a lower perimeter of the STI. The drain region is positioned further from the gate than the source region.

1 . A transistor comprising: 
 a gate on a substrate;    a channel region in said substrate below said gate;    a source region in said substrate on one side of said channel region, a drain region in said substrate on an opposite side of said channel region from said source region;    a shallow trench isolation (STI) region in said substrate between said drain region and said channel region, wherein said STI region comprises a trench in said substrate, sidewall spacers along walls of said trench, and an isolation material between said spacers filling said trench; and    a drain extension below said STI region.    
   
   
       2 . The transistor in  claim 1 , wherein said drain extension is positioned along a bottom of said STI region and along a portion of sides of said STI.  
   
   
       3 . The transistor in  claim 2 , wherein portions of said drain extension along said bottom of said STI comprise different dopant implants that said portions of said drain extensions along said sides of said STI.  
   
   
       4 . The transistor in  claim 2 , wherein portions of said drain extensions along sides of said STI extend from said bottom of said STI to a position partially up said sides of said STI.  
   
   
       5 . The transistor in  claim 1 , wherein said STI region is below a portion of said gate.  
   
   
       6 . The transistor in  claim 1 , wherein said drain extension provides a conductive path between said drain region and said channel region around a lower perimeter of said STI.  
   
   
       7 . The transistor in  claim 1 , wherein said drain region is positioned further from said gate than said source region.  
   
   
       8 . The transistor in  claim 1 , further comprising a gate oxide below said gate, wherein said STI region forms a portion of said gate oxide.