Method and structure to process thick and thin fins and variable fin to fin spacing

Abstract

Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

1 . An integrated circuit structure comprising: 
 a substrate;    a plurality of semiconductor fins comprising at least one adjacent pair of first semiconductor fins having a first width and at least one adjacent pair of second semiconductor fins having a second width, wherein said second width is greater than said first width and wherein spacing between said semiconductor fins is variable; and    a non-planar field effect transistor comprising said plurality of said semiconductor fins.    
     
     
         2 . The integrated circuit structure of  claim 1 , wherein said spacing between said adjacent pair of said first semiconductor fins is greater than said spacing between said adjacent pair of said second semiconductor fins.  
     
     
         3 . The integrated circuit structure of  claim 1 , wherein said spacing between said adjacent pair of said second semiconductor fins is less than current state of the art minimum lithographic dimensions.  
     
     
         4 . The integrated circuit structure of  claim 1 , wherein said plurality of semiconductor fins further comprises at least one adjacent pair of third semiconductor fins having a third width that is greater than said second width.  
     
     
         5 . The integrated circuit structure of  claim 3 , wherein said spacing between said adjacent pair of said second semiconductor fins is greater than said spacing between said adjacent pair of said third semiconductor fins.  
     
     
         6 . The integrated circuit structure of  claim 3 , wherein said plurality of semiconductor fins further comprises at least one adjacent pair of fourth semiconductor fins having a fourth width that is less than said second width and greater than said first width.  
     
     
         7 . The integrated circuit structure of  claim 1 , wherein said semiconductor fins comprise one of silicon and silicon germanium and said substrate comprises an oxide layer.  
     
     
         8 . An integrated circuit structure comprising: 
 a substrate;    a plurality of semiconductor fins comprising at least one adjacent pair of first semiconductor fins having a first width and at least one adjacent pair of second semiconductor fins having a second width, wherein said second width is greater than said first width and wherein spacing between said semiconductor fins is variable; and    a plurality of non-planar field effect transistors each comprising at least one of said semiconductor fins.    
     
     
         9 . The integrated circuit structure of  claim 8 , wherein said spacing between said adjacent pair of said first semiconductor fins is greater than said spacing between said adjacent pair of said second semiconductor fins.  
     
     
         10 . The integrated circuit structure of  claim 8 , wherein said spacing between said adjacent pair of said second semiconductor fins is less than current state of the art minimum lithographic dimensions.  
     
     
         11 . The integrated circuit structure of  claim 8 , wherein said plurality of semiconductor fins further comprises at least one adjacent pair of third semiconductor fins having a third width that is greater than said second width.  
     
     
         12 . The integrated circuit structure of  claim 11 , wherein said spacing between said adjacent pair of said second semiconductor fins is greater than said spacing between said adjacent pair of said third semiconductor fins.  
     
     
         13 . The integrated circuit structure of  claim 11 , wherein said plurality of semiconductor fins further comprises at least one adjacent pair of fourth semiconductor fins having a fourth width that is less than said second width and greater than said first width.  
     
     
         14 . The integrated circuit structure of  claim 8 , wherein said semiconductor fins comprise one of silicon and silicon germanium and said substrate comprises an oxide layer.  
     
     
         15 . An integrated circuit structure comprising: 
 a substrate;    a plurality of semiconductor fins comprising at least one adjacent pair of first semiconductor fins having a first width and at least one adjacent pair of second semiconductor fins having a second width, wherein said second width is greater than said first width and wherein spacing between said semiconductor fins is variable; and    a non-planar field effect transistor comprising said plurality of said semiconductor fins,    wherein said plurality of semiconductor fins further comprises at least one adjacent pair of third semiconductor fins having a third width that is greater than said second width.    
     
     
         16 . The integrated circuit structure of  claim 15 , wherein said spacing between said adjacent pair of said first semiconductor fins is greater than said spacing between said adjacent pair of said second semiconductor fins.  
     
     
         17 . The integrated circuit structure of  claim 15 , wherein said spacing between said adjacent pair of said second semiconductor fins is less than current state of the art minimum lithographic dimensions.  
     
     
         18 . The integrated circuit structure of  claim 17 , wherein said spacing between said adjacent pair of said second semiconductor fins is greater than said spacing between said adjacent pair of said third semiconductor fins.  
     
     
         19 . The integrated circuit structure of  claim 17 , wherein said plurality of semiconductor fins further comprises at least one adjacent pair of fourth semiconductor fins having a fourth width that is less than said second width and greater than said first width.  
     
     
         20 . The integrated circuit structure of  claim 15 , wherein said semiconductor fins comprise one of silicon and silicon germanium and said substrate comprises an oxide layer.