Etch features with reduced line edge roughness

Abstract

A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the sidewalls of the photoresist features by performing for a plurality of cycles. Each cycle comprises depositing a layer on the photoresist layer wherein the deposited layer has a thickness between a monolayer to 20 nm. Features are etched into the layer through the photoresist features. The photoresist layer and sidewall layer are stripped.

1 - 13 . (canceled)  
   
   
       14 . A semiconductor device formed by the method comprising: 
 forming a photoresist layer over the layer;    patterning the photoresist layer to form photoresist features with photoresist sidewalls;    forming a sidewall layer with a thickness less than 100 nm over the sidewalls of the photoresist features, comprising performing for a plurality of cycles, wherein each cycle comprises depositing a layer on the photoresist layer wherein the deposited layer has a thickness between a monolayer to 20 nm;    etching features into the layer through the photoresist features; and    stripping the photoresist layer and sidewall layer.    
   
   
       15 - 19 . (canceled)  
   
   
       20 . A semiconductor device formed by the method, comprising: 
 forming a patterned photoresist layer to over the etch layer to form photoresist features with photoresist sidewalls;    forming a sidewall layer with a thickness less than 100 nm over the sidewalls of the photoresist features, comprising performing for a plurality of cycles, wherein each cycle comprises: 
 depositing a layer on the photoresist layer wherein the deposited layer has a thickness between a monolayer to 20 nm; and  
 etching back the deposited layer to remove parts of the deposited layer formed over bottoms of the photoresist features, while leaving a sidewall layer;  
   etching features into the etch layer through the photoresist features; and    stripping the photoresist layer and sidewall layer, wherein the depositing the layer on the photoresist layer, the etching back, the etching features, and stripping are done in situ in a single plasma chamber.    
   
   
       21 . The semiconductor device, as recited in  claim 14 , wherein each cycle of the forming the sidewall layer, further comprises etching back the deposited layer to remove parts of the deposited layer formed over bottoms of the photoresist features, while leaving a sidewall layer.  
   
   
       22 . The semiconductor device, as recited in  claim 21 , wherein the depositing the layer on the photoresist layer, comprises performing at least one of atomic layer deposition, chemical vapor deposition, sputtering deposition, plasma deposition, and plasma enhanced chemical vapor deposition, with a bias potential of less than 120 volts.  
   
   
       23 . The semiconductor device, as recited in  claim 22 , further comprising heating the substrate to a temperature between −80° C. to 120° C. during the depositing the layer on the photoresist layer.  
   
   
       24 . The semiconductor device, as recited in  claim 23 , wherein the depositing the sidewall layer over the sidewalls is performed for between 3 and 10 cycles.  
   
   
       25 . The semiconductor device, as recited in  claim 24 , the depositing the layer on the photoresist layer comprises depositing a layer of at least one of polymer, TEOS, SiO 2 , Si 3 N 2 , SiC, Si, Al 2 O 3 , AlN, Cu, HfO 2 , Mo, Ta, TaN, TaO 2 , Ti, TiN, TiO 2 , TiSiN, and W.  
   
   
       26 . The semiconductor device, as recited in  claim 25 , further comprising performing a break through etch to etch through any remaining deposited layer.  
   
   
       27 . The semiconductor device, as recited in  claim 26 , wherein the depositing the layer on the photoresist layer, the etching back, the break through, and the etching features are done in situ in a single plasma chamber.  
   
   
       28 . The semiconductor device, as recited in  claim 21 , wherein the etching back further removes parts of the deposited layer over a top of the photoresist layer.  
   
   
       29 . The semiconductor device, as recited in  claim 21 , wherein the depositing the layer on the photoresist layer, comprises performing at least one of chemical vapor deposition, sputtering deposition, plasma deposition, and plasma enhanced chemical vapor deposition.  
   
   
       30 . The semiconductor device, as recited in  claim 29 , wherein the depositing the layer on the photoresist layer further comprises providing a bias potential of less than 120 volts.  
   
   
       31 . The semiconductor device, as recited in  claim 30 , wherein the depositing the layer on the photoresist layer, the etching back, the break through, and the etching features are done in situ in a single plasma chamber.  
   
   
       32 . The semiconductor device, as recited in  claim 21 , wherein the depositing the layer on the photoresist layer, the etching back, and the etching features are done in situ in a single plasma chamber.  
   
   
       33 . The semiconductor device, as recited in  claim 20 , wherein the depositing the layer on the photoresist layer, comprises performing at least one of atomic layer deposition, chemical vapor deposition, sputtering deposition, plasma deposition, and plasma enhanced chemical vapor deposition, with a bias potential of less than 120 volts.  
   
   
       34 . The semiconductor device, as recited in  claim 33 , further comprising heating the substrate to a temperature between 80° C. to 120° C. during the depositing the layer on the photoresist layer.  
   
   
       35 . The semiconductor device, as recited in  claim 20 , wherein the depositing the sidewall layer over the sidewalls is performed for between 3 and 10 cycles.  
   
   
       36 . The semiconductor device, as recited in  claim 20 , wherein the depositing the layer on the photoresist layer comprises depositing a layer of at least one of polymer, TEOS, SiO 2 , Si 3 N 2 , SiC, Si, Al 2 O 3 , AlN, Cu, HfO 2 , Mo, Ta, TaN, TaO 2 , Ti, TiN, TiO 2 , TiSiN, and W.