Method of fabricating semiconductor device

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

1 .- 21 . (canceled)  
   
   
       22 . A semiconductor device having a MISFET forming region and a gate lead-out region formed on a main surface of a semiconductor substrate, comprising: 
 a first trench formed in the semiconductor substrate at the MISFET forming region;    a gate insulating film of a MISFET formed in the first trench;    a gate electrode of the MISFET formed on the gate insulating film and in the first trench,    a second trench formed in the semiconductor substrate at the gate lead-out region and extending in a first direction,    wherein the MISFET forming region is divided into plural island regions,    the first trench is terminated by the second, trench such that the second trench is connected to the first trench at an end portion of the first trench, such that the plural island regions are arranged in the first direction at the end portion of the first trench and such that the plural island regions are spaced from each other in the first direction, by the first trench and by the second trench, at the end portion of the first trench; and    a gate lead-out electrode formed in the second trench and outside the second trench at the gate lead-out region,    wherein the gate lead-out region is located in a peripheral region of the main surface of the semiconductor substrate, and    the gate lead-out electrode is integrally formed with the gate electrode.    
   
   
       23 . A semiconductor device according to  claim 22 , 
 wherein the MISFET forming region is located on only one side of the gate lead-out region.    
   
   
       24 . A semiconductor device according to  claim 22 , 
 wherein the gate lead-out electrode and the gate electrode are comprised of a silicon film.    
   
   
       25 . A semiconductor device according to  claim 22 , 
 wherein the plural island regions are arranged in a matrix.    
   
   
       26 . A semiconductor device according to  claim 22 , 
 wherein a source region of the MISFET is formed in the semiconductor substrate, and    wherein a drain region of the MISFET is formed in the semiconductor substrate and is formed under the source region such that a channel forming region is arranged, in a depth direction of the semiconductor substrate, between the source region and the drain region.    
   
   
       27 . A semiconductor device having a MISFET forming region and a gate lead-out region formed on a main surface of a semiconductor substrate, comprising: 
 a first trench formed in the semiconductor substrate at the MISFET forming region;    a gate insulating film of a MISFET formed in the first trench;    a gate electrode of the MISFET formed on the gate insulating film and in the first trench;    a second trench formed in the semiconductor substrate at the gate lead-out region and extending in a first direction,    wherein the MISFET forming region is divided into plural island regions,    the first trench is terminated by the second trench such that the second trench is connected to the first trench at an end portion of the first trench, such that the plural island regions are arranged in the first direction at the end portion of the first trench and such that the plural island regions are spaced from each other in the first direction, by the first trench and by the second trench, at the end portion of the first trench; and    a gate lead-out electrode formed in the second trench and outside the second trench at the gate lead-out region,    wherein the gate lead-out region is located in a peripheral region of the main surface of the semiconductor substrate, and    the gate lead-out electrode is integrally formed with the gate electrode,    the plural island regions are arranged in a matrix,    a source region of the MISFET is formed in the semiconductor substrate, and    a drain region of the MISFET is formed in the semiconductor substrate and is formed under the source region such that a channel forming region is arranged, in a depth direction of the semiconductor substrate, between the source region and the drain region.    
   
   
       28 . A semiconductor device according to  claim 27 , 
 wherein the MISFET forming region is located on only one side of the gate lead-out region.    
   
   
       29 . A semiconductor device according to  claim 27 , 
 wherein the gate lead-out electrode and the gate electrode are comprised of a silicon film.