Method of fabricating semiconductor device

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

1 .- 21 . (canceled)  
   
   
       22 . A semiconductor device having a MISFETs forming region and a gate lead-out region on a main surface of a semiconductor substrate, comprising: 
 a plurality of first trenches in the semiconductor substrate in the MISFETs forming region;    a plurality of gate insulating films of the MISFETs formed in the plurality of the first trenches;    a plurality of gate electrodes of the MISFETs formed on the plurality of the gate insulating films;    a second trench formed in the gate lead-out region, the second trench being crossing to the first trenches; and    a gate lead-out electrode formed in the second trench and outside the second trench in the gate lead-out region,    wherein the gate lead-out region is located in a peripheral region of the main surface of the semiconductor substrate,    the second trench is connected at each end portion of the first trenches,    the first trenches are terminated by the second trench,    the gate lead-out electrode is integrally formed with the plurality of gate electrodes, and    the top surface of the gate electrode is lower than the top surface of the semiconductor substrate in the gate lead-out region.    
   
   
       23 . A semiconductor device according to  claim 22 , 
 wherein the MISFETs forming region is located on only one side of the gate lead-out region.    
   
   
       24 . A semiconductor device according to  claim 22 , 
 wherein the gate lead-out electrode and the gate electrode are comprised of a silicon film.    
   
   
       25 . A semiconductor device having a MISFETs forming region and a gate lead-out region formed on a main surface of a semiconductor substrate, comprising: 
 first trenches formed in the semiconductor substrate at the MISFETs forming region;    gate insulating films formed in the first trenches;    gate electrodes formed on the gate insulating films and in the first trenches;    a second trench formed in the semiconductor substrate at the gate lead-out region and extending in a first direction,    wherein the MISFETs forming region is divided into plural island regions,    the first trenches are terminated by the second trench such that the second trench is connected to the first trenches at an end portion of the first trenches, such that the plural island regions are arranged in the first direction at the end portion of the first trenches and such that the plural island regions are spaced from each other in the first direction, by the first trenches at the end portion of the first trenches; and    a gate lead-out electrode formed in the second trench and outside the second trench at the gate lead-out region,    wherein the gate lead-out region is located in a peripheral region of the main surface of the semiconductor substrate,    the gate lead-out electrode is integrally formed with the gate electrode, and    the top surface of the gate electrode is lower than the top surface of the semiconductor substrate in the gate lead-out region.    
   
   
       26 . A semiconductor device according to  claim 25 , 
 wherein source regions are formed in the plural island regions,    wherein a drain region is formed in the semiconductor substrate and is formed under the source regions such that channel forming regions are arranged, in a depth direction of the semiconductor substrate, between the source region and the drain region, and    wherein the source regions are electrically connected to each other by a source electrode formed over the main surface of the semiconductor substrate.    
   
   
       27 . A semiconductor device according to  claim 25 , 
 wherein the MISFETs forming region is located on only one side of the gate lead-out region.    
   
   
       28 . A semiconductor device according to  claim 25 , 
 wherein the gate lead-out electrode and the gate electrode are comprised of a silicon film.    
   
   
       29 . A semiconductor device having a MISFETs forming region and a gate lead-out region formed on a main surface of a semiconductor substrate, comprising: 
 first trenches formed in the semiconductor substrate at the MISFETs forming region;    gate insulating films formed in the first trenches;    gate electrodes formed on the gate insulating films and in the first trenches;    a second trench formed in the semiconductor substrate at the gate lead-out region and extending in a first direction,    wherein the MISFETs forming region is divided into plural island regions,    the first trenches are terminated by the second trench such that the second trench is connected to the first trenches at an end portion of the first trenches, such that the plural island regions are arranged in the first direction at the end portion of the first trenches and such that the plural island regions are spaced from each other in the first direction, by the first trenches at the end portion of the first trenches; and    a gate lead-out electrode formed in the second trench and outside the second trench at the gate lead-out region,    wherein the gate lead-out region is located in a peripheral region of the main surface of the semiconductor substrate,    the gate lead-out electrode is integrally formed with the gate electrode,    the top surface of the gate electrode is lower than the top surface of the semiconductor substrate in the gate lead-out region;    source regions are formed in the plural island regions;    a drain region is formed in the semiconductor substrate and is formed under the source regions such that channel forming regions are arranged, in a depth direction of the semiconductor substrate, between the source region and the drain region,    a source electrode is formed over the main surface of the semiconductor substrate and electrically connected to the source regions; and    a drain electrode is formed over a back surface of the semiconductor substrate and electrically connected to the drain region.    
   
   
       30 . A semiconductor device according to  claim 29 , 
 wherein the MISFETs forming region is located on only one side of the gate lead-out region.    
   
   
       31 . A semiconductor device according to  claim 29 , 
 wherein the gate lead-out electrode and the gate electrode are comprised of a silicon film.