Non-volatile semiconductor memory devices

Abstract

A non-volatile memory device includes a tunneling insulating layer on a semiconductor substrate, a charge storage layer, a blocking insulating layer, and a gate electrode. The charge storage layer is on the tunnel insulating layer and has a smaller band gap than the tunnel insulating layer and has a greater band gap than the semiconductor substrate. The blocking insulating layer is on the charge storage layer and has a greater band gap than the charge storage layer and has a smaller band gap than the tunnel insulating layer. The gate electrode is on the blocking insulating layer.

1 . A non-volatile memory device, comprising: 
 a tunnel insulating layer on a semiconductor substrate;    a charge storage layer on the tunnel insulating layer, a band gap of the charge storage layer is smaller than a band gap of the tunnel insulating layer and greater than a band gap of the semiconductor substrate;    a blocking insulating layer on the charge storage layer, a band gap of the blocking insulating layer is greater than the band gap of the charge storage layer and smaller than the band gap of the tunnel insulating layer; and    a gate electrode on the blocking insulating layer.    
   
   
       2 . The non-volatile memory device of  claim 1 , wherein a potential barrier between a conduction band of the tunnel insulating layer and a conduction band of the charge storage layer is greater than a potential barrier between a conduction band of the blocking insulating layer and the conduction band of the charge storage layer.  
   
   
       3 . The non-volatile memory device of  claim 2 , wherein a potential barrier between a valence band of the tunnel insulating layer and a valence band of the charge storage layer is greater than a potential barrier between a valence band of the blocking insulating layer and the valence band of the charge storage layer.  
   
   
       4 . The non-volatile memory device of  claim 2 , wherein the band gap of the blocking insulating layer is 8.3 eV or less.  
   
   
       5 . The non-volatile memory device of  claim 1 , wherein a potential barrier between a valence band of the tunnel insulating layer and a valence band of the charge storage layer is greater than a potential barrier between a valence band of the blocking insulating layer and the valence band of the charge storage layer.  
   
   
       6 . The non-volatile memory device of  claim 5 , wherein the band gap of the blocking insulating layer is 8.3 eV or less.  
   
   
       7 . The non-volatile memory device of  claim 1 , wherein the band gap of the blocking insulating layer is 8.3 eV or less.  
   
   
       8 . The non-volatile memory device of  claim 1 , wherein the blocking insulating layer comprises a dielectric layer and a first oxide layer, and wherein a band gap of the dielectric layer is greater than the band gap of the charge storage layer and smaller than the band gap of the tunnel insulating layer, and a band gap of the first oxide layer is greater than the band gap of the dielectric layer.  
   
   
       9 . The non-volatile memory device of  claim 8 , wherein the first oxide layer is located between the dielectric layer and the gate electrode.  
   
   
       10 . The non-volatile memory device of  claim 8 , wherein the dielectric layer is located between the first oxide layer and the gate electrode.  
   
   
       11 . The non-volatile memory device of  claim 10 , wherein the blocking insulating layer further comprises a second oxide layer between the dielectric layer and the gate electrode, and wherein a band gap of the second oxide layer is greater than the band gap of the dielectric layer.  
   
   
       12 . The non-volatile memory device of  claim 8 , wherein a potential barrier between a conduction band of the first oxide layer and a conduction band of the gate electrode is greater than a potential barrier between a conduction band of the tunnel insulating layer and a conduction band of the semiconductor substrate.  
   
   
       13 . A non-volatile memory device, comprising: 
 a tunnel insulating layer on a semiconductor substrate;    a charge storage layer on the tunnel insulating layer, a conduction band of the charge storage layer is lower than a conduction band of the tunnel insulating layer, a band gap of the charge storage layer is greater than a band gap of the semiconductor substrate;    a blocking insulating layer on the charge storage layer, a conduction band of the blocking insulating layer is higher than the conduction band of the charge storage layer and is lower than the conduction band of the tunnel insulating layer; and    a gate electrode on the third insulating layer.    
   
   
       14 . The non-volatile memory device of  claim 13 , wherein a band gap of the tunnel insulating layer and a band gap of the blocking insulating layer are greater than a band gap of the charge storage layer.  
   
   
       15 . The non-volatile memory device of  claim 14 , wherein the band gap of the blocking insulating layer is 8.3 eV or less.  
   
   
       16 . The non-volatile memory device of  claim 13 , wherein a valence band of the charge storage layer is higher than a valence band of the blocking insulating layer and a valence band of the tunnel insulating layer.  
   
   
       17 . The non-volatile memory device of  claim 13 , wherein the blocking insulating layer comprises a dielectric layer and a first oxide layer, and wherein a conduction band of the dielectric layer is higher than the conduction band of the charge storage layer and lower than the conduction band of the tunnel insulating layer, and a conduction band of the first oxide layer is higher than the conduction band of the dielectric layer.  
   
   
       18 . The non-volatile memory device of  claim 17 , wherein the first oxide layer is located between the dielectric layer and the gate electrode.  
   
   
       19 . The non-volatile memory device of  claim 17 , wherein the dielectric layer is located between the first oxide layer and the gate electrode.  
   
   
       20 . The non-volatile memory device of  claim 19 , wherein the blocking insulating layer further comprises a second oxide layer between the dielectric layer and the gate electrode, and wherein a conduction band of the second oxide layer is higher than the conduction band of the dielectric layer.