Nonvolatile semiconductor memory device having double floating gate structure and method of manufacturing the same

Abstract

The nonvolatile semiconductor memory device includes a non-planar active region with floating gates disposed on opposite sides of the active region. A control gate overlaps the floating gates and a portion of the active region.

1 . A nonvolatile semiconductor memory device, comprising: 
 an active region over a substrate;    a first floating gate at a first sidewall of the active region;    a first coupling gate insulating layer between the first floating gate and the first sidewall of the active region;    a second floating gate at a second sidewall of the active region, the second sidewall opposite to the first sidewall;    a second coupling gate insulating layer between the second floating gate and the second sidewall of the active region;    an insulating layer between the active region and a word line; and    a source and a drain in the active region.    
     
     
         2 . The device of  claim 1 , wherein the active region extends in a first direction over the substrate, and the word line extends in a second direction perpendicular to the first direction.  
     
     
         3 . The device of  claim 1 , wherein the first and second sidewalls of the active region provide channels when voltages are applied to the word line and the source.  
     
     
         4 . The device of  claim 3 , wherein one channel is adjacent to the first coupling gate insulating layer and another channel is adjacent to the second coupling gate insulating layer.  
     
     
         5 . The device of  claim 1 , wherein 
 the first floating gate has a first overlap portion where the word line overlaps a side and top surface of the first floating gate so as to overlap at least three corners of the first floating gate; and    the second floating gate has a second overlap portion where the word line overlaps a side and top surface of the second floating gate so as to overlap at least three corners of the second floating gate.    
     
     
         6 . The device of  claim 5 , further comprising: 
 a first interpoly tunneling insulating layer between the word line and the first overlap portion to overlap the at least three corners of the first floating gate; and    a second interpoly tunneling insulating layer between the word line and the second overlap portion to overlap the at least three corners of the second floating gate.    
     
     
         7 . The device of  claim 5 , wherein the insulating layer between the word line and the active region is on the active region between the first overlap portion and the second overlap portion.  
     
     
         8 . The device of  claim 1 , wherein the active region is formed of a silicon island.  
     
     
         9 . A nonvolatile semiconductor memory device, comprising: 
 a plurality of silicon islands over a substrate;    a plurality of first floating gates, each associated with one of the plurality of silicon islands and at a first sidewall of the associated silicon island;    first coupling gate insulating layers, each between an associated first floating gate and the associated silicon island;    a plurality of second floating gates, each associated with one of the plurality of silicon islands and at a second sidewall of the associated silicon island, the second sidewall opposite to the first sidewall;    second coupling gate insulating layers, each between an associated second floating gate and the associated silicon island; and    at least one word line over the silicon islands and overlapping portions of the plurality of first floating gates and portions of the plurality of second floating gates.    
     
     
         10 . The device of  claim 9 , further comprising: 
 an insulating layer between the word line and each silicon island.    
     
     
         11 . The device of  claim 9 , wherein 
 each of the silicon islands includes a source and at least one drain.    
     
     
         12 . The device of  claim 11 , further comprising: 
 a source line over the silicon islands and parallel to the word line, the source line being electrically connected to the source in each of the silicon islands.    
     
     
         13 . The device of  claim 12 , wherein the word line and the source line each include a metal silicide layer.  
     
     
         14 . The device of  claim 9 , wherein the silicon islands are formed on an insulated substrate.  
     
     
         15 . A nonvolatile semiconductor memory device, comprising: 
 an active region of a first conductivity type, the active region extending in a first direction on a first insulating layer over a substrate, the active region having a square sectional bar shape, the active region including a source and at least one drain, each of a second conductivity type opposite to the first conductivity type, and the active region including a channel region for providing channels perpendicular to an upper surface of the substrate between the source and the drain;    a first floating gate and a second floating gate on the first insulating layer and facing each other with the active region therebetween;    a first coupling gate insulating layer between the active region and the first floating gate;    a second coupling gate insulating layer between the active region and the second floating gate; and    a first word line over a portion of the active region with a second insulating layer therebetween.    
     
     
         16 . The device of  claim 15 , further comprising: 
 a bit line connected to the drain and extending perpendicular to a lengthwise direction of the word line; and    the first floating gate and the second floating gate defining one memory cell, which has only one contact point with the bit line and only one contact point with the word line.    
     
     
         17 . The device of  claim 16 , wherein the channels are two channels having surfaces that are perpendicular to the upper surface of the substrate along both sidewalls of the channel region when voltages are applied to the word line and the source.  
     
     
         18 . The device of  claim 17 , wherein the two channels are adjacent to the first coupling gate insulating layer and the second coupling gate insulating layer.  
     
     
         19 . The device of  claim 15 , wherein the word line extends in a second direction perpendicular to the first direction.  
     
     
         20 . The device of  claim 15 , wherein 
 the first floating gate includes a first overlap portion facing the word line and the second floating gate includes a second overlap portion facing the word line; and    the word line has a plurality of recessed surfaces so as to surround the first overlap portion and the second overlap portion.    
     
     
         21 . The device of  claim 20 , wherein the word line surrounds at least three corners of the first floating gate and at least three corners of the second floating gate.  
     
     
         22 . The device of  claim 20 , further comprising: 
 a first interpoly tunneling insulating layer between the word line and the first overlap portion to surround the at least three corners of the first floating gate; and    a second interpoly tunneling insulating layer between the word line and the second overlap portion to surround the at least three corners of the second floating gate.    
     
     
         23 . The device of  claim 20 , wherein the second insulating layer is on the channel region between the first overlap portion and the second overlap portion.  
     
     
         24 . The device of  claim 15 , wherein 
 the source, the drain, the first floating gate, and the second floating gate define a memory cell with respect to the active region; and    a plurality of active regions are on the substrate with each of the active regions including first and second memory cells.    
     
     
         25 . The device of  claim 24 , wherein the first and second memory cells of each active region have a common source.  
     
     
         26 . The device of  claim 24 , wherein the first word line and a second word line are over the plurality of active regions, the first word line is connected to the first memory cell of each active region and the second word line is connected to the second memory cell of each active region.  
     
     
         27 . The device of  claim 24 , wherein 
 the plurality of active regions are arranged in the lengthwise direction of the word line, and    the sources in the active regions are connected to each other via a source line that extends parallel to the word line.    
     
     
         28 . The device of  claim 27 , wherein at least one of the word line and the source line include a metal silicide layer.  
     
     
         29 . The device of  claim 15 , wherein 
 the first insulating layer is formed of a buried oxide layer formed in a silicon on insulator substrate; and    the active region is formed of silicon.    
     
     
         30 . The device of  claim 29 , wherein 
 the first floating gate and the second floating gate each have a floating gate length that extends in the first direction; and    the upper surface of the active region has a width of ⅔ the floating gate length.    
     
     
         31 . A nonvolatile semiconductor memory device, comprising: 
 a plurality of first memory cells, each of the plurality of first memory cells including, 
 a semiconductor layer extending in a first direction over an insulating layer, which is on a substrate, the semiconductor layer including a source and a first drain, and the semiconductor layer providing a channel region between the source and the first drain;  
 a first floating gate adjacent a first sidewall of the channel region;  
 a second floating gate adjacent a second sidewall of the channel region, the second sidewall opposite to the first sidewall; and  
 a control gate at least partially over the first and second floating gates.  
   
     
     
         32 . The device of  claim 31 , wherein the semiconductor layer provides for a plurality of channels between the source and drain in the channel region.  
     
     
         33 . The device of  claim 32 , wherein for each first memory cell, 
 the first and second sidewalls are perpendicular to the first insulating layer; and    an upper surface of the semiconductor layer is parallel to the first insulating layer; and    the channel region provides for a first channel and a second channel, which are adjacent to the first floating gate and the second floating gate, respectively, and are parallel to the first and second sidewalls.    
     
     
         34 . The device of  claim 33 , wherein for each first memory cell, 
 the first floating gate and the second floating gate each have a floating gate length that extends in the first direction; and    the upper surface of the semiconductor layer has a width of ⅔ the floating gate length.    
     
     
         35 . The device of  claim 33 , further comprising: 
 a first coupling gate insulating layer and a second coupling gate insulating layer, which are on the first and second sidewalls, respectively, of the semiconductor layer adjacent to the first channel and the second channel and between the semiconductor layer and the first and second floating gates, respectively.    
     
     
         36 . The device of  claim 32 , wherein for each first memory cell, 
 the first and second sidewalls are perpendicular to the first insulating layer;    an upper surface of the semiconductor layer is parallel to the first insulating layer; and    the control gate is over a portion of the upper surface of the semiconductor layer.    
     
     
         37 . The device of  claim 36 , further comprising: 
 a second insulating layer on the portion of the upper surface of the semiconductor layer between the control gate and semiconductor layer.    
     
     
         38 . The device of  claim 31 , wherein for each first memory cell, the first floating gate and the second floating gate each have at least three corners covered by the control gate.  
     
     
         39 . The device of  claim 31 , wherein for each first memory cell, the source and the drain each have a higher dopant concentration than in the channel region.  
     
     
         40 . The device of  claim 31 , further comprising: 
 a plurality of second memory cells, each of the second memory cells associated with one of the first memory cells and formed from a same semiconductor layer as the associated first memory cell, each second memory cell having a same structure as the associated first memory cell.    
     
     
         41 . The device of  claim 40 , wherein each second memory cell and the associated first memory cell have a common source.  
     
     
         42 . The device of  claim 41 , further comprising: 
 a source line connected to the common sources.    
     
     
         43 . The device of  claim 42 , further comprising: 
 a first word line parallel to the source line and connected to each control gate of the first memory cells; and    a second word line parallel to the source line and connected to each control gate of the second memory cells.    
     
     
         44 . A nonvolatile memory cell, comprising: 
 a semiconductor layer over a substrate;    a first floating gate at a first side of the semiconductor layer;    a second floating gate at a second side of the semiconductor layer, the second side opposite to the first side; and    a control gate over the first and second floating gates and a portion of the semiconductor layer such that the control gate covers at least three corners of each of the first and second floating gates.    
     
     
         45 . A method of manufacturing a memory cell, comprising: 
 forming a semiconductor layer over a substrate;    forming first and second floating gates at first and second sides of the semiconductor layer, the first side being opposite to the second side; and    forming a control gate over the first and second floating gates and a portion of the semiconductor layer such that the control gate covers at least three corners of each of the first and second floating gates.