Pipelined semiconductor memories and systems

Abstract

The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.

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       18 . A semiconductor memory device, comprising: 
 a plurality of independently addressable banks to store data; and    a Global Address Supervisor coupled to said plurality of independently addressable banks, wherein said Global Address Supervisor is configured to continuously receive a sequence of row and column addresses addressing selected ones of said banks, and to steer said continuously received row and column addresses to the addressed banks of said plurality of independently addressable banks in a manner that avoids bank conflicts.    
   
   
       19 . The semiconductor memory device as recited in  claim 18 , wherein if a bank of said plurality of independently addressable banks is unavailable, then said Global Address Supervisor is configured to hold a received address addressing the unavailable bank in a staging area.  
   
   
       20 . The semiconductor memory device as recited in  claim 19 , wherein said Global Address Supervisor is further configured to release an address held in the staging area to the addressed bank of said plurality of independently addressable banks after the addressed bank becomes available.  
   
   
       21 . The semiconductor memory device as recited in  claim 18 , wherein the semiconductor memory device is configured to be coupled to separate read and write buses to receive said row and column addresses through said separate read and write busses.  
   
   
       22 . A method for operating a memory device comprising: 
 receiving a sequence of row and column addresses addressing selected ones of a plurality of memory banks of the memory device; and    steering said received sequence of row and column addresses to the addressed bank of said plurality of independently addressable banks in a manner that avoids bank conflicts.    
   
   
       23 . The method as recited in  claim 22  further comprising: 
 holding a received address addressing an unavailable bank in a staging area.    
   
   
       24 . The method as recited in  claim 23  further comprising: 
 releasing an address held in the staging area to the addressed bank after the addressed bank becomes available.    
   
   
       25 . The method as recited in  claim 22 , wherein said receiving comprises receiving said row and column addresses through separate read and write busses.  
   
   
       26 . The apparatus of  claim 18  wherein said continuously received row and column addresses are toggled on both rising and falling edges of a clock signal.  
   
   
       27 . The apparatus of  claim 18  further comprising an SRAM register and wherein the Global Address Supervisor is coupled to said independently addressable banks via the SRAM register.  
   
   
       28 . The apparatus of  claim 18  further comprising independent read and write paths coupled to said independently addressable banks for independently reading or writing data to the independently addressable banks.  
   
   
       29 . The apparatus of  claim 28  further comprising a plurality of buffers coupling the independent read and write paths to the independently addressable banks, the plurality of buffers including at least one buffer coupled to the read path and at least one buffer coupled to the write path.  
   
   
       30 . The apparatus of  claim 29  wherein the plurality of buffers are SRAM devices.  
   
   
       31 . The apparatus of  claim 29  wherein the plurality of buffers comprise either a plurality of read buffers coupled to the read path or a plurality of write buffers coupled to the write path for maintaining simultaneous multiple open pages of the independently addressable banks.  
   
   
       32 . The method of  claim 22  further comprising toggling the continuous sequence of row and column addresses on both rising and falling edges of a clock signal.  
   
   
       33 . The semiconductor memory device of  claim 18 , wherein the Global Address Supervisor is configured to map said continuously received row and column addresses to the addressed banks of said plurality of independently addressable banks in a manner that avoids bank conflicts.  
   
   
       34 . The method of  claim 22  further comprising mapping said received sequence of row and column addresses to the addressed bank of said plurality of independently addressable banks in a manner that avoids bank conflicts.