One Mask High Density Capacitor for Integrated Circuits

Abstract

An on-chip decoupling capacitor ( 106 ) and method of fabrication. The decoupling capacitor ( 104 ) is integrated at the top metal interconnect level ( 104 ) and may be implemented with only one additional masking layer. The decoupling capacitor ( 106 ) is formed on a copper interconnect line ( 104 a ). An aluminum cap layer ( 118 ) provides electrical connection to the top electrode ( 112 ) of the decoupling capacitor ( 106 ).

1 - 10 . (canceled)  
   
   
       11 . A method of fabricating an integrated circuit comprising the steps of: 
 providing a semiconductor body having a plurality of metal interconnect levels formed thereon, a topmost one of said plurality of metal interconnect levels having a first and a second metal interconnect line; and    forming a decoupling capacitor over said topmost one of said plurality of metal interconnect levels.    
   
   
       12 . The method of  claim 11 , wherein a bottom electrode of said decoupling capacitor is electrically connected to said first metal interconnect line.  
   
   
       13 . The method of  claim 11 , further comprising the step of forming a metal capping layer over said topmost one of said plurality of metal interconnect levels and said decoupling capacitor, wherein said metal capping layer electrically connects a top electrode of said decoupling capacitor to said second metal interconnect line.  
   
   
       14 . The method of  claim 11 , wherein said step of forming said decoupling capacitor comprises the steps of: 
 forming a bottom electrode material over said topmost one of said plurality of metal interconnect levels;    forming a capacitor dielectric over said bottom electrode material; and    forming a top electrode material over said capacitor dielectric.    
   
   
       15 . The method of  claim 14 , wherein said top electrode comprises TaN, said capacitor dielectric comprises tantalum-oxide, and said bottom electrode comprises TaN.  
   
   
       16 . The method of  claim 14 , wherein said step of forming a capacitor dielectric comprises the steps of: 
 depositing a layer of tantalum-oxide over said bottom electrode; and    annealing said layer of tantalum-oxide in oxygen to reduce impurities and increase the oxygen content.    
   
   
       17 . A method of fabricating an integrated circuit comprising the steps of: 
 providing a semiconductor body having a plurality of copper interconnect levels formed therein, a topmost one of said plurality of copper interconnect levels having a first and a second copper interconnect line;    forming a bottom electrode material over said topmost one of said plurality of copper interconnect levels, said bottom electrode in direct contact with said first copper interconnect level;    forming a capacitor dielectric over said bottom electrode material;    forming a top electrode material over said capacitor dielectric;    patterning and etching the capacitor stack    forming an aluminum cap layer over said topmost one of said plurality of copper interconnect levels and said top electrode, wherein said aluminum cap layer electrically connects said top electrode to said second copper interconnect line.    
   
   
       18 . The method of  claim 17 , wherein said top electrode comprises TaN, said capacitor dielectric comprises tantalum-oxide, and said bottom electrode comprises TaN.  
   
   
       19 . The method of  claim 17 , wherein said step of forming a capacitor dielectric comprises the steps of: 
 depositing a layer of tantalum-oxide over said bottom electrode; and    annealing said layer of tantalum-oxide in oxygen.    
   
   
       20 . The method of  claim 17 , wherein said top and bottom electrodes each comprise one or more layers of material selected from the group consisting of TaN, TiN, Ir, Ru, and Ta.