Array-Processed Stacked Semiconductor Packages

Abstract

One embodiment of the invention is a semiconductor system ( 1400 ) of arrays ( 1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate ( 1411, 1412, etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound ( 1412, 1422, etc.), which adheres to the substrate, embeds the connected components. Metal posts ( 1431, 1432, etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.

1 . A semiconductor system comprising:
 a first array of packaged devices including:
 a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines and vertical vias, attachment sites on the first surface, and terminals on the first and the second surface; 
 semiconductor components attached to the substrate attachment sites; 
 electrical connections from the components to substrate terminals on the first surface; 
 encapsulation compound adhering to the first substrate surface and embedding the connected components; 
 metal posts traversing the encapsulation compound vertically to connect terminals on the first substrate surface with pads on the encapsulation surface; and 
   solder bodies attached to the pads;   a second array of packaged devices having a sheet-like substrate with a third and a fourth surface, terminals on the fourth surface matching the solder-covered pads of the first array; and   the second array aligned and connected with the first array at the matching terminals and pads to form a 3-dimensional system of packaged devices.   
     
     
         2 . The system according to  claim 1  further including a distribution of the encapsulation compound so that the thickness of the compound over the components is about equal to the thickness of the substrate. 
     
     
         3 . The system according to  claim 1  wherein the semiconductor components include chips of active and passive devices, and stacks of chips. 
     
     
         4 . The system according to  claim 1  wherein the electrical connections include flip-chip assembly, wire bonds, or both. 
     
     
         5 . The system according to  claim 1  wherein the assembled arrays are singulated vertically into stacks of packaged devices. 
     
     
         6 . A semiconductor system comprising:
 a first array of packaged devices including:
 a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface; 
 an array of assembly sites on the first surface, each site including a first and a second set of terminals on the first surface, and a third set of terminals on the second surface; 
 a semiconductor component, having a thickness and I/O ports, flip-attached to each assembly site using metal studs for interconnecting the chip ports to the first set terminals; 
 metal posts at least on portions of the second set terminals, the posts being about vertical to the first surface, having a height taller than the component thickness, and matching the locations of the third set terminals; 
 encapsulation compound adhering to the first substrate surface and embedding the connected components so that the compound has a thickness about equal to the post height; 
 a pad capping each post; and 
 reflow metal on the pads, the metal having a first reflow temperature; 
   a second array of packaged devices having a sheet-like substrate with a third and a fourth surface, terminals on the fourth surface matching the reflow metal covered pads of the first array; and   the second array aligned and connected with the first array at the matching terminals and pads to form a 3-dimensional system of packaged devices.   
     
     
         7 . The system according to  claim 6  further including reflow metal bodies on the third set contact pads of the first array, the bodies having a second reflow temperature lower than the first reflow temperature. 
     
     
         8 . The system according to  claim 6  further including a thickness of the encapsulation compound over the components about equal to the sheet thickness of the substrate. 
     
     
         9 . The system according to  claim 6  wherein the assembled arrays are singulated vertically into stacks of packaged devices. 
     
     
         10 . A semiconductor system comprising:
 a first array of packaged devices including:
 a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface; 
 an array of assembly sites on the first surface, each site including a chip-attachment location, a first and a second set of terminals on the first surface and a third, a fourth, and a fifth set of terminals on the second surface; 
 a semiconductor component, having a thickness, an active surface with a first and second set of I/O ports, and a passive surface, attached with its passive surface to each attachment location; 
 a bond wire span with a height between each first set port and the respective first set terminal; 
 a bond wire loop on each second set port, the loops reaching the same height as the wire spans; 
 metal posts on the second set terminals, the posts being about vertical to the first surface, having a height taller than the sum of the component thickness and the wire loop height, and matching the locations of the third set terminals; 
 encapsulation compound adhering to the first substrate surface and embedding the connected components so that the compound has a thickness about equal to the post height; 
 a pad capping each post, wire span top, and wire loop top, the pads on the wire span tops matching the locations of the fourth set terminals, the pads on the wire loop tops matching the locations of the fifth set terminals; and 
 reflow metal on the pads, the metal having a first reflow temperature; 
   a second array of packaged devices having a sheet-like substrate with a third and a fourth surface, terminals on the fourth surface matching the reflow metal covered pads of the first array; and   the second array aligned and connected with the first array at the matching terminals and pads to form a 3-dimensional system of packaged devices.   
     
     
         11 . The system according to  claim 10  further including reflow metal bodies on the third, the fourth, and the fifth set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature. 
     
     
         12 . The system according to  claim 10  further including a thickness of the encapsulation compound over the components about equal to the sheet thickness of the substrate. 
     
     
         13 . The system according to  claim 10  wherein the assembled arrays are singulated vertically into stacks of packaged devices. 
     
     
         14 . A semiconductor system comprising:
 a first array of packaged devices including:
 a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface; 
 an array of assembly sites on the first surface, each site including a first, a second, and a third set of terminals on the first surface, and a fourth, a fifth, and a sixth set of terminals on the second surface; 
 a first semiconductor component, having a first thickness, an active surface with I/O ports, and a passive surface, flip-attached to each assembly site using metal studs for interconnecting the component ports to the first set terminals; 
 a second component, having a second thickness, an active surface with a first and a second set of I/O ports, and a passive surface, attached with its passive surface to the passive surface of a first component; 
 a bond wire span with a height between each first set port and the respective second set terminal; 
 a bond wire loop on each second set port, the loops reaching the same height as the wire spans; 
 metal posts at least on portions of the third set terminals, the post being about vertical to the first surface, having a height taller than the sum of the first and second component thicknesses and the wire loop height, and matching the locations of the fourth set terminals; 
 encapsulation compound adhering to the first substrate surface and embedding the connected components so that the compound has a thickness about equal to the post height; 
 a pad capping each post, wire span top, and wire loop top, the pads on the wire span tops matching the locations of the fifth set terminals, the pads on the wire loop tops matching the locations of the sixth set terminals; and 
 reflow metal on the pads, the metal having a first reflow temperature; 
   a second array of packaged devices having a sheet-like substrate with a third and a fourth surface, terminals on the fourth surface matching the reflow metal covered aligned with the first array, the contact pads on the first array; and   the second array aligned and connected with the first array at the matching terminals and pads to form a 3-dimensional system of packaged devices.   
     
     
         15 . The system according to  claim 14  further including reflow metal bodies on the fourth, the fifth, and the sixth set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature. 
     
     
         16 . The system according to  claim 14  further including a thickness of the encapsulation compound over the components about equal to the sheet thickness of the substrate. 
     
     
         17 . The system according to  claim 14  wherein the assembled arrays are singulated vertically into stacks of packaged devices. 
     
     
         18 . A method for fabricating a semiconductor system comprising the steps of:
 fabricating a first array of packaged devices including the steps of:
 providing a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines and vertical vias; 
 forming attachment sites on the first surface, each site including terminals on the first and the second surface; 
 providing semiconductor components having a thickness and I/O ports; 
 attaching the components to the substrate attachment sites; 
 connecting the components electrically to the substrate terminals on the first surface; 
 forming metal posts at least on portions of the second set terminals, the posts being vertical to the first surface and having a height taller than the component thickness, the post locations matching at least portions of the terminals on the second surface; 
 embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound having a thickness about equal to the post height; 
 depositing pads on each post; and 
 depositing reflow metal on the pads, the metal having a reflow temperature; 
   fabricating a second array of packaged devices by the same steps as fabricating the first array, the substrate of the second array having a third and a fourth surface, the terminals on the fourth surface matching the solder-covered pads of the first array, and the reflow metal having the same reflow temperature as for the first array; and   assembling a semiconductor system including the steps of:
 aligning and contacting the terminals on the fourth surface of the second array with the reflow metal-covered pads of the first array; and 
 applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array. 
   
     
     
         19 . The method according to  claim 18  wherein the step of embedding the components is performed so that the encapsulation compound has a thickness over the components about equal the sheet thickness of the substrate. 
     
     
         20 . A method for fabricating a semiconductor system, comprising the steps of:
 fabricating a first array of packaged devices including the steps of:
 providing a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface; 
 forming an array of assembly sites on the first surface, each site including a first and a second set of terminals on the first surface, and a third set of terminals on the second surface; 
 providing semiconductor components having a thickness and I/O ports; 
 flip-attaching a component to each assembly site using metal studs for interconnecting the component ports to the first set terminals; 
 forming metal posts at least on portions of the second set terminals, the posts being about normal to the first surface, having a height taller than the component thickness, and matching the locations of the third set pads; 
 embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound having a thickness at least equal to the post height; 
 exposing the top surface of the posts; 
 depositing a pad on each exposed post surface; and 
 depositing reflow metal on the pads, the metal having a reflow temperature; 
   fabricating a second array of packaged devices by the same steps as fabricating the first array, the substrate having a third and a fourth surface, terminals on the fourth surface matching the reflow metal-covered pads of the first array, and the reflow metal having the same reflow temperature as in the first array; and   assembling a semiconductor system, including the steps of:
 aligning and contacting the terminals on the fourth surface with the reflow metal-covered pads of the first array; and 
 applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array. 
   
     
     
         21 . The method according to  claim 20  wherein the step of embedding the components is performed so that the encapsulation compound has a thickness over the components about equal to the sheet thickness of the substrate. 
     
     
         22 . The method according to  claim 20  further including the step of depositing reflow metal bodies on the third set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature. 
     
     
         23 . The method according to  claim 20  further including the steps of fabricating a third to an n th  array of packaged devices, including depositing reflow metals on all pads, further the steps of assembling an array of stacked semiconductor packages by aligning the arrays of devices respectively, and applying thermal energy to reflow the reflow metals between all arrays in one step so that all arrays are concurrently electrically connected and a 3-dimensional system of packaged components is created. 
     
     
         24 . The method according to  claim 20  further including the step of sawing the assembled arrays vertically so that individual stacks of packaged devices are singulated. 
     
     
         25 . A method for fabricating a semiconductor system, comprising the steps of:
 fabricating a first array of packaged devices including the steps of:
 providing a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface; 
 forming an array of assembly sites, each site including a component attach location, a first and a second set of terminals on the first surface, and a third, a fourth, and a fifth set of terminals on the second surface; 
 providing semiconductor components having a thickness, an active surface with a first and a second set of I/O ports, and a passive surface; 
 attaching the passive surface of a component to each substrate attachment location; 
 forming spans of bond wire to electrically connect the first set ports to the first set terminals, the top of all spans in a plane; 
 forming loops of bond wire on the second set ports, the top of all loops in the same plane as the span tops; 
 forming metal posts on the second set terminals to match the locations of the third set terminals, the posts being about normal to the first surface and having a height to reach the plane of the wire span tops and wire loop tops; 
 embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound having a thickness at least equal to the post height; 
 exposing the top surface of the posts, the wire loops, and the wire spans; 
 depositing a pad on the surface of each exposed top of posts, wire spans, and wire loops, the pads on the wire span tops matching the locations of the fourth set terminals, the pads on the wire loop tops matching the locations of the fifth set terminals; and 
 depositing reflow metal on the pads, the metal having a reflow temperature; 
   fabricating a second array of packaged devices by the same steps as fabricating the first array, the substrate having a third and fourth surface, terminals on the fourth surface matching reflow-metal covered pads of the first array, and the reflow metal having the same reflow temperature as in the first array; and   assembling a semiconductor system, including the steps of:
 aligning and contacting the terminals on the fourth surface with the reflow metal-covered pads of the first array; and 
 applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array. 
   
     
     
         26 . The method according to  claim 25  wherein the step of embedding the components is performed so that the encapsulation compound has a thickness over the components about equal to the sheet thickness of the substrate. 
     
     
         27 . The method according to  claim 25  further including the step of depositing reflow metal bodies on the third, fourth and fifth set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature. 
     
     
         28 . The method according to  claim 25  further including the steps of fabricating a third to an n th  array of packaged devices, including depositing reflow metals on all pads, further the steps of assembling an array of stacked semiconductor packages steps by aligning the arrays of devices respectively, and applying thermal energy to reflow the reflow metals between all arrays in one step so that all arrays are concurrently electrically connected and a 3-dimensional system of packaged components is created. 
     
     
         29 . The method according to  claim 25  further including the step of sawing the assembled arrays vertically so that individual stacks of packaged devices are singulated. 
     
     
         30 . A method for fabricating a semiconductor system, comprising the steps of:
 fabricating a first array of packaged devices including the steps of:
 providing a sheet-like substrate having a first and a second surface and a thickness, the substrate made of insulating material integral with conductive horizontal lines between the surfaces and conductive vertical vias extending from the first to the second surface; 
 forming an array of assembly sites, each site including a first, a second, and a third set of terminals on the first surface, and a fourth, a fifth, and a sixth set of terminals on the second surface; 
 providing first semiconductor components having a first thickness, an active surface with I/O ports, and a passive surface; 
 flip-attaching a first component to each assembly site using metal studs for interconnecting the ports to the first set terminals; 
 providing second semiconductor components having a second thickness, an active surface with a first and a second set of I/O ports, and a passive surface; 
 attaching the passive surface of a second component to the passive surface of each first component; 
 forming spans of bond wire to electrically connect the first set ports to the second set terminals, the top of all spans in a plane; 
 forming loops of bond wire on the second set ports, the top of all loops in the same plane as the span tops; 
 forming metal posts at least on portions of the second set terminals to match the locations of the fourth set terminals, the posts being about normal to the first surface and having a height to reach the plane of the wire span tops and wire loop tops; 
 embedding the connected components in encapsulation compound adhering to the first substrate surface, the compound having a thickness at least equal to the post height; 
 exposing the top surface of the posts, the wire loops, and the wire spans; 
 depositing a pad on the surface of each exposed top of posts, wire spans, and wire loops, the pads on the wire span tops matching the locations of the fifth set terminals, the pads on the wire loop tops matching the locations of the sixth set terminals; and 
 depositing reflow metal on the pads, the metal having a reflow temperature; 
   fabricating a second array of packaged subsystems by the same steps as fabricating the first array, the substrate having a third and fourth surface, terminals on the fourth surface matching reflow-metal covered pads of the first array, and the reflow metal having the same reflow temperature as in the first array; and   assembling a semiconductor system, including the steps of:
 aligning and contacting the terminals on the fourth surface with the reflow metal-covered pads of the first array; and 
 applying thermal energy to reflow the reflow metals of both arrays to bond and electrically connect the first and the second array. 
   
     
     
         31 . The method according to  claim 30  wherein the step of embedding the components is performed so that the encapsulation compound has a thickness over the components about equal to the sheet thickness of the substrate. 
     
     
         32 . The method according to  claim 30  further including the step of depositing reflow metal bodies on the fourth, fifth, and sixth set terminals of the first array, the bodies having a second reflow temperature lower than the first reflow temperature. 
     
     
         33 . The method according to  claim 30  further including the steps of fabricating a third to an n th  array of packaged devices, including depositing reflow metals on all pads, further the steps of assembling an array of stacked semiconductor package by aligning the arrays of devices respectively, and applying thermal energy to reflow the reflow metals between all arrays in one step so that all arrays are concurrently electrically connected and a 3-dimensional system of packaged components is created. 
     
     
         34 . The method according to  claim 30  further including the step of sawing the assembled arrays vertically so that individual stacks of packaged devices are singulated.