SELF-ALIGNED PROCESS FOR NANOTUBE/NANOWIRE FETs

Abstract

A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.

1 . A method of fabricating a semiconductor substrate comprising the steps of: 
 providing a structure that includes at least one gate stack on a surface of a layer of at least one one-dimensional nanostructure;    forming a source/drain metal on said structure including at least said layer of at least one one-dimensional nanostructure; and    forming a metal carbide by reacting said source/drain metal with said layer of at least one one-dimensional nanostructure.    
     
     
         2 . The method of  claim 1  wherein said layer of at least one one-dimensional nanostructure comprises at least one nanotube.  
     
     
         3 . The method  claim 1  wherein said layer of at least one one-dimensional nanostructure comprises at least one nanowire.  
     
     
         4 . The method of  claim 1  wherein said layer of at least one one-dimensional nanostructure comprises a combination of nanotubes and nanowires.  
     
     
         5 . The method of  claim 1  wherein said layer of at least one one-dimensional nanostructure comprises a C-based nanomaterial.  
     
     
         6 . The method of  claim 1  wherein said layer of at least one one-dimensional nanostructure is formed by arc-discharge, laser ablation of a carbon target, or chemical vapor deposition.  
     
     
         7 . The method of  claim 1  wherein said structure includes a substrate located beneath said layer of one-dimensional nanostructures.  
     
     
         8 . The method of  7  wherein said substrate comprises a semiconductor layer and a dielectric layer, said dielectric layer having optional regions of a C-containing compound embedded therein.  
     
     
         9 . The method of  claim 1  further comprising doping said portion of said layer of at least one one-dimensional nanostructure not protected by said at least one gate stack prior to forming said source/drain metal, said doping comprises electrostatic doping, ion implantation, or gas phase doping.  
     
     
         10 . The method of  claim 1  wherein said forming said source/drain metal comprises selecting at least one of Al, Si, Sc, Ti, V, Cr, Mn, Fe, Y, Zr, Nb, Mo, Hf, Ta or W and depositing the same.  
     
     
         11 . The method of  claim 10  wherein said depositing comprises an atomic layer deposition process or deposition from a carbon-containing target.  
     
     
         12 . The method of  claim 1  further comprising forming a metal compound that functionalizes portions of the layer of at least one one-dimensional nanostructure not protected by said at least one gate stack prior to forming said source/drain metal.  
     
     
         13 . The method of  claim 1  wherein said forming said metal carbide comprises annealing and removing remaining source/drain metal that does not react with said exposed portion of said layer of at least one one-dimensional nanostructure.  
     
     
         14 . The method of  claim 13  wherein said annealing is performed in an inert ambient at a temperature of about 600° C. or above.  
     
     
         15 . The method of  claim 1  wherein said metal carbide is aligned to an edge of the gate stack including a portion of layer of at least one one-dimensional nanostructure.  
     
     
         16 . The method of  claim 1  wherein said metal carbide is formed by anneal, said annealing also causes at least one of said one-dimensional nanostructures to embedded within a conducting compound region.