Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress Liner

Abstract

In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

1 . A semiconductor device comprising: 
 a substrate;    a PMOSFET formed on the substrate;    an NMOSFET formed on the substrate; and    a dual stress liner including a first portion formed on the PMOSFET and a second portion formed on the NMOSFET, the first portion having a first stress and the second portion having a second stress smaller than the first stress, wherein a stress liner is formed on the PMOSFET and the NMOSFET, and a stress of a portion of the stress liner formed on the NMOSFET is relaxed by selectively exposing the portion of the stress liner to an ultraviolet light to form the dual stress.    
   
   
       2 . The semiconductor device of  claim 1 , wherein each of the PMOSFET and the NMOSFET comprises: 
 a gate insulating layer formed on the substrate;    a gate electrode formed on the gate insulating layer; and    impurity regions to be used as source/drain regions, which are formed at surface portions of the substrate adjacent to the gate electrode.    
   
   
       3 . The semiconductor device of  claim 2 , wherein each of the PMOSFET and the NMOSFET further comprises silicide layers formed on a top portion of the gate electrode and surface portions of the impurity regions.  
   
   
       4 . The semiconductor device of  claim 1 , wherein the first stress is a first compressive stress, and the second stress is a second compressive stress smaller than the first compressive stress.  
   
   
       5 . The semiconductor device of  claim 1 , wherein the dual stress liner comprises silicon nitride.  
   
   
       6 . A light exposure apparatus comprising: 
 a stage for supporting a substrate, wherein a PMOSFET and an NMOSFET are formed on the substrate, and a stress liner having a first stress is formed on the PMOSFET and the NMOSFET;    a photomask having a light transmitting section corresponding to a portion of the stress liner on the NMOSFET;    an illumination optical system for illuminating the photomask with an illumination light; and    a projection optical system for exposing the portion of the stress liner on the NMOSFET to a projection light transmitted through the light transmitting section so that the portion of the stress liner on the NMOSFET has a second stress smaller than the first stress, wherein a stress portion of the portion of the stress liner on the NMOSFET is relaxed by selectively exposing the portion of the stress liner on the NMOSFET to the projection light.    
   
   
       7 . The light exposure apparatus of  claim 6 , further comprising a heater for the substrate.  
   
   
       8 . The light exposure apparatus of  claim 6 , further comprising a vacuum chamber for receiving the stage.  
   
   
       9 . The light exposure apparatus of  claim 6 , wherein the illumination light comprises an ultraviolet light.