US2008042237A1PendingUtilityA1

Semiconductor device and method of manufacturing the same

Assignee: RENESAS TECHNOLGY CORPPriority: Dec 19, 2003Filed: Oct 17, 2007Published: Feb 21, 2008
Est. expiryDec 19, 2023(expired)· nominal 20-yr term from priority
H10W 10/181H10W 10/061H10W 10/17H10W 10/014H10P 90/1906H10D 30/601H10D 30/0227H10D 30/0212H10D 86/201H10D 86/80H10D 86/01H10D 84/811H10D 1/47H10D 1/20H10D 84/40H10D 84/00H10D 84/80H10D 84/817
48
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a potion of the OSI layer and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising: 
 an SOI substrate including a substrate serving as a base, a buried oxide film provided on said substrate, and an SOI layer provided on said buried oxide film;    plural first isolation films provided in a main surface of said SOI layer in a first region defined on said SOI substrate, with a portion of said SOI layer interposed between the plural first isolation films; and    plural resistive elements provided on said plural first isolation films in said first region, respectively, wherein    at least a portion of each of said plural first isolation films passes through said SOI layer and reaches said buried oxide film to include a full-trench isolation structure.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein 
 each of said plural first isolation films includes only said full-trench isolation structure in section.    
   
   
       3 . The semiconductor device according to  claim 1 , wherein 
 said SOI layer includes impurities with a concentration which allows said SOI layer to be fully depleted in said first region.    
   
   
       4 . A semiconductor device comprising: 
 an SOI substrate including a substrate serving as a base, a buried oxide film provided on said substrate, and an SOI layer provided on said buried oxide film;    plural first isolation films provided in a main surface of said SOI layer in a first region defined on said SOI substrate, with portions of said SOI layer interposed between the plural first isolation films; and    plural resistive elements provided via insulating films on said portions of said SOI layer interposed between said plural first isolation films, respectively, wherein    at least a portion of each of said plural first isolation films passes through said SOI layer and reaches said buried oxide film to include a full-trench isolation structure.    
   
   
       5 . The semiconductor device according to  claim 4 , wherein 
 each of said plural first isolation films includes only said full-trench isolation structure in section.    
   
   
       6 . The semiconductor device according to  claim 4 , wherein 
 said SOI layer includes impurities with a concentration which allows said SOI layer to be fully depleted in said first region.    
   
   
       7 . The semiconductor device according to  claim 4 , further comprising 
 a MOS transistor provided in a second region different from said first region, wherein    said MOS transistor includes a gate insulating film provided on said SOI layer in said second region, and    a thickness of each of said insulating films on said SOI layer in said first region is larger than that of said gate insulating film.    
   
   
       8 . The semiconductor device according to  claim 1 , further comprising: 
 an inductor provided above said SOI substrate, wherein    said first region is located under said inductor.    
   
   
       9 . The semiconductor device according to  claim 4 , further comprising: 
 an inductor provided above said SOI substrate, wherein    said first region is located under said inductor.

Join the waitlist — get patent alerts

Track US2008042237A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.