Semiconductor devices and methods of fabricating the same

Abstract

Embodiments include a semiconductor device comprising: a pad formed on an insulating layer and having an electric connection region with external components; and a protective insulating layer which has an aperture for exposing the electric connection region. The protective insulating layer may include a first insulating layer and a second insulating layer, and side surfaces of these insulating layers are exposed to the aperture. At least part of the side surfaces surrounding the electric connection region have a tapered configuration at an acute angle to a top surface of the pad. This semiconductor device not only enables reduction of the fabrication steps, but also provides a reliable passivation structure for a pad with sufficient thickness and stress relaxation characteristics.

1 . A bonding pad structure comprising: 
 a bonding pad formed over a portion of a substrate area; and    an insulating layer on the bonding pad;    the insulating layer including a first layer and a second layer, the first layer positioned between the bonding pad and the second layer, the second layer including a tapered side surface having an acute angle to a surface of the bonding pad;    the bonding pad including an area that is uncovered by the insulating layer; and    the first layer including an upper surface region uncovered by the second layer.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the first layer has a tapered side surface having an acute angle to the surface of the bonding pad, and the first layer tapered side surface acute angle is greater than that of the second layer tapered side surface.  
     
     
         3 . The semiconductor device of  claim 1 , wherein the distance between an upper edge of the first layer and a lower edge of the second layer tapered side surface is no greater than 3 μm.  
     
     
         4 . The semiconductor device of  claim 1 , wherein the distance between an upper edge of the first layer and a lower edge of the second layer tapered side surface is no greater than 1 μm.  
     
     
         5 . The semiconductor device of  claim 1 , wherein the bonding pad includes a barrier layer positioned on the area that is uncovered by the insulating layer.  
     
     
         6 . The semiconductor device of  claim 5 , wherein the barrier layer is also positioned on the second layer tapered side surface, and wherein the barrier layer is also positioned on the first layer upper surface region uncovered by the second layer.  
     
     
         7 . The bonding pad structure of  claim 1 , the first layer has a thickness that is less than that of the second layer.  
     
     
         8 . A bonding pad structure comprising: 
 a bonding pad formed over a portion of a substrate area; and    an insulating layer on the bonding pad;    the insulating layer including a first layer and a second layer, the first layer positioned between the bonding pad and the second layer, the first layer including a tapered side surface having an acute angle to a surface of the bonding pad, the second layer including a tapered side surface having an acute angle to a surface of the bonding pad, the first layer tapered side surface acute angle being greater than the second layer tapered side surface acute angle;    the bonding pad including an area that is uncovered by the insulating layer; and    the first layer including an upper surface region uncovered by the second layer, the upper surface region uncovered by the second layer extending a distance between an upper end of the first layer tapered side surface and a lower end of the second layer tapered side surface, the distance being no greater than 3 μm.    
     
     
         9 . The semiconductor device of  claim 8 , wherein the distance is no greater than 1 μm.  
     
     
         10 . The semiconductor device of  claim 8 , wherein the bonding pad includes a barrier layer positioned on the area that is uncovered by the insulating layer.  
     
     
         11 . The bonding pad structure of  claim 8 , the first layer having a thickness in the range of 400 nm to 600 nm, the second layer having a thickness that is greater than that of the first layer and in the range of 600 nm to 1400 nm.  
     
     
         12 . A semiconductor device comprising: 
 an electrode formed on a bonding pad over a portion of a substrate area; and    an insulating layer surrounding a portion of the electrode;    the insulating layer including a first layer and a second layer, the first layer positioned between the bonding pad and the second layer, the second layer including a tapered side surface having an acute angle to a surface of the bonding pad,    the bonding pad including an area that is uncovered by the insulating layer, the electrode formed on the area, and    the first layer including an upper surface region uncovered by the second layer.    
     
     
         13 . The semiconductor device of  claim 12 , wherein the first layer has a tapered side surface having an acute angle to the surface of the bonding pad, and wherein the first layer tapered side surface acute angle is greater than that of the second layer tapered side surface.  
     
     
         14 . The semiconductor device of  claim 12 , wherein the electrode is positioned above the upper surface region uncovered by the second layer.  
     
     
         15 . The semiconductor device of  claim 13 , wherein the electrode is positioned above the first layer tapered side surface, and wherein the electrode is positioned above the second layer tapered side surface.  
     
     
         16 . The semiconductor device of  claim 13 , wherein the first layer upper surface region uncovered by the second layer extends a distance between an upper end of the first layer tapered side surface and a lower end of the second layer tapered side surface, the distance being no greater than 3 μm.  
     
     
         17 . The semiconductor device of  claim 12 , wherein the distance between an upper edge of the first layer and a lower edge of the second layer tapered side surface is no greater than 1 μm.  
     
     
         18 . The semiconductor device of  claim 13 , wherein the bonding pad includes a barrier layer positioned on the area that is uncovered by the insulating layer.  
     
     
         19 . The semiconductor device of  claim 12 , wherein the barrier layer is also positioned directly between the electrode and the first and second tapered side surfaces, and wherein the barrier layer is also positioned directly between the electrode and the first layer upper surface region uncovered by the second layer.