Method for Processing a Structure of a Semiconductor Component, and Structure in a Semiconductor Component

Abstract

A method is used for processing a structure of a semiconductor component. The structure has at least one partial structure to be etched, in particular a sublithographic partial structure. The at least one partial structure has at least one structure to be etched with at least one lateral etch stop to which at least one mask is applied in such a way that at least one lateral etch stop is covered by the mask and afterward at least one of the structures to be etched is etched away isotropically as far as at least one etch stop using the mask. The at least one mask and the at least one etch stop are then removed.

1 . A method for forming an integrated circuit, the method comprising: 
 providing a structure that has at least one sublithographic partial structure wherein the at least one sublithographic partial structure has at least one structure to be etched with at least one lateral etch stop;    applying at least one mask in such a way that at least one lateral etch stop is covered by the mask;    etching at least one of the structures to be etched isotropically as far as at least one lateral etch stop using the mask; and    removing the at least one mask and removing the at least one etch stop.    
   
   
       2 . The method as claimed in  claim 1 , wherein the at least one sublithographic partial structure has at least one line structure having a sublithographic width.  
   
   
       3 . The method as claimed in  claim 1 , wherein the at least one lateral etch stop comprises a plurality of lateral etch stops produced by a sublithographic method, each lateral etch stop having an identical width.  
   
   
       4 . The method as claimed in  claim 1 , wherein the at least one sublithographic partial structure has at least one line structure having a critical dimension that is less than 0.25*λ/NA or is less than a minimum half-pitch that can be achieved in practice by means of the exposure tool.  
   
   
       5 . The method as claimed in  claim 1 , wherein the at least one sublithographic partial structure has a width between 10 nm and 100 nm.  
   
   
       6 . The method as claimed in  claim 1 , wherein the at least one sublithographic partial structure has a plug structure having a minimum edge-to-edge distance of between 50 nm and 80 nm.  
   
   
       7 . The method as claimed in  claim 1 , wherein the at least one lateral etch stop is a part of a layer deposited in a previous method step as a liner layer and/or spacer layer above the partial structure to be etched.  
   
   
       8 . The method as claimed in  claim 7 , wherein the lateral etch stop has a thickness between 1 and 60 nm.  
   
   
       9 . The method as claimed in  claim 1 , wherein the covering of the mask over the at least one lateral etch stop is at least 5 nm.  
   
   
       10 . The method as claimed in  claim 1 , wherein etching isotropically is effected selectively with respect to the at least one lateral etch stop.  
   
   
       11 . The method as claimed in  claim 1 , wherein the at least one lateral etch stop comprises nitride.  
   
   
       12 . The method as claimed in  claim 1 , wherein removing the at least one lateral etch stop comprises performing an HF etch.  
   
   
       13 . The method as claimed in  claim 1 , wherein etching at least one of the structures comprises a chloride etch.  
   
   
       14 . The method as claimed in  claim 1 , wherein the mask is constructed in multilayer fashion.  
   
   
       15 . The method as claimed in  claim 14 , wherein the mask comprises a resist layer, a BARC layer and/or a hard mask layer.  
   
   
       16 . The method as claimed in  claim 14 , wherein the mask comprises a hard mask layer comprising SiON, Si 3 N 4  and/or amorphous silicon.  
   
   
       17 . The method as claimed in  claim 1 , further comprising performing an anisotropic incipient etch prior to the isotropic etching away of the at least one structure to be etched.  
   
   
       18 . The method as claimed in  claim 1 , wherein etching isotropically of the at least one structure to be etched as far as at least one etch stop using the previously applied mask and the removal of the at least one mask and removal of the at least one etching stop lead to a self-aligned removal of the structure to be etched.  
   
   
       19 . The method as claimed in  claim 1 , wherein the lithography for producing the structure is effected with a wavelength of 248 nm, 193 nm, 157 nm or 13.4 nm.  
   
   
       20 . The method as claimed in  claim 1 , wherein the at least one partial structure to be etched and/or the at least one lateral etch stop have a regular pattern.  
   
   
       21 . The method as claimed in  claim 1 , wherein forming an integrated circuit comprises forming a DRAM chip, an NROM chip or a microprocessor.  
   
   
       22 . An integrated circuit that includes a structure wherein the structure has at least one sublithographic partial structure wherein the at least one sublithographic partial structure has at least one structure to be etched with at least one lateral etch stop that is part of a dielectric spacer structure, wherein the dielectric spacer structure electrically insulates parts of the at least one partial structure from one another.  
   
   
       23 . The integrated circuit as claimed in  claim 22 , wherein the at least one lateral etch stop comprises an oxide and/or a nitride.  
   
   
       24 . The integrated circuit as claimed in  claim 22 , wherein the lateral etch stop has a thickness between 10 and 60 nm.  
   
   
       25 . The integrated circuit as claimed in  claim 22 , wherein the at least one lateral etch stop surrounds a line structure and/or a plug structure.  
   
   
       26 . The integrated circuit as claimed in  claim 22 , wherein the integrated circuit comprises a DRAM chip, an NROM chip or a microprocessor or an intermediate product for a DRAM chip, an NROM chip or a microprocessor.