Semiconductor device with double barrier film

Abstract

A semiconductor device comprising a first insulation layer, a second insulation layer, a first barrier film, a second barrier film, a diffusion layer. The device further comprises an upper contact hole, a lower contact hole, and a contact plug. The upper contact hole penetrates the second insulation layer and has a bottom in the second barrier film. The bottom has a width greater than a trench made in the first insulation layer, as measured in a direction crossing the widthwise direction of the trench. The lower contact hole penetrates the first insulation layer and first barrier film, communicates with the first contact hole via the trench and is provided on the diffusion layer. The upper portion of the lower contact hole has the same width as the trench. The contact plug is provided in the upper contact hole and lower contact hole.

1 . A semiconductor device comprising: 
 a transistor having a gate electrode that is provided via a gate insulation film on a semiconductor substrate, a metal layer that is provided on the gate electrode, and diffusion layers that are separately provided in the semiconductor substrate such that the gate electrode is provided on a region lying between the diffusion layers, each of the diffusion layers serving as a source or a drain;    a first barrier film that is provided on the diffusion layer, which serves as the source or drain of the transistor, and on side walls of the transistor;    a first insulation layer that is provided on the first barrier film;    a second barrier film that is continuously provided on the metal layer and on the first insulation layer;    a second insulation layer that is provided on the second barrier film;    an opening portion that is provided in the second barrier film and is located over the diffusion layer;    a first contact plug that continuously penetrates the second insulation layer, the first insulation layer and the first barrier layer through the opening portion, and is provided on the diffusion layer; and    a second contact plug that continuously penetrates the second insulation layer, the second barrier film and the metal layer and establishes electrical connection to the gate electrode.    
   
   
       2 . The device according to  claim 1 , wherein the second barrier film has a greater thickness than the first barrier film.  
   
   
       3 . The device according to  claim 1 , wherein the first and second barrier films function as barriers against reactions between the first insulation layer and the metal layer and between the second insulation layer and the metal layer.  
   
   
       4 . The device according to  claim 1 , wherein the first and second barrier films function as stoppers at a time of forming the first contact plug and the second contact plug.  
   
   
       5 . The device according to  claim 1 , further comprising a memory cell array that comprises: 
 a memory cell row; and    a select transistor that selects the memory cell row,    wherein the transistor is a peripheral transistor that is provided in a peripheral circuit formed near the memory cell array.    
   
   
       6 . The device according to  claim 5 , wherein the memory cell row is arranged in a first direction and includes a plurality of series-connected memory cell transistors having sources and drains shared, each of the plurality of memory cell transistors comprising: 
 a floating electrode provided via the gate insulation film on the semiconductor substrate;    an inter-gate insulation film provided on the floating electrode;    a control electrode provided on the inter-gate insulation film,    wherein the peripheral transistor transfers a write voltage to the control electrode.