Three dimensional device integration method and integrated device

Abstract

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

1 . An integrated structure, comprising: 
 a first layer of bondable material with a surface roughness less than about 1 nm disposed on a first element having a first substrate;    a second element having a surface roughness of less than about 1 nm;    said first layer of bondable material directly bonded to said second element without fusing said first layer of bondable material to said second element; and    a portion of said first element being removed to leave a remaining portion of said first element after said bonding.    
     
     
         2 . A structure as recited in  claim 1 , wherein said first layer of bondable material comprises a first silicon oxide layer.  
     
     
         3 . A structure as recited in  claim 1 , wherein said first element comprises a semiconductor device.  
     
     
         4 . A structure as recited in  claim 1 , wherein said first element comprises a first semiconductor device having metallic contact structures.  
     
     
         5 . A structure as recited in  claim 4 , wherein said second element comprises a second semiconductor device.  
     
     
         6 . A structure as recited in  claim 5 , comprising: 
 a connection member connecting said first and second semiconductor devices.    
     
     
         7 . A structure as recited in  claim 1 , wherein said first layer has a surface roughness of no more than 0.5 nm.  
     
     
         8 . A structure as recited in  claim 1 , comprising: 
 a second layer of bonding material disposed on said second element, said second layer of bonding material having a surface roughness less than about 1 nm;    said first and second layers being in direct contact; and    said first layer directly bonded to said second layer.    
     
     
         9 . A structure as recited in  claim 1 , comprising: 
 a bond strength between said first and second elements sufficient to permit removing said portion.    
     
     
         10 . A structure as recited in claim  30 , wherein said second element comprises a silicon substrate.  
     
     
         11 . A structure as recited in  claim 1 , wherein: 
 said first element has a smaller area than an area of said second element.    
     
     
         12 . An integration method, comprising: 
 bonding a first surface of a semiconductor device having a first substrate and an exposed peripheral side surface to an element having a second substrate with a second surface;    removing a portion of said first substrate to expose a third surface of said first semiconductor device;    forming an insulating material on said element and on said peripheral side surface;    forming a first via in said insulating material to expose said element;    forming a second via in said first substrate to expose said device;    connecting said first semiconductor device and said element by forming a connection extending over said peripheral side surface and through said first and second vias.    
     
     
         13 . A method as recited in  claim 12 , wherein: 
 said first semiconductor device has a smaller area than an area of said element.    
     
     
         14 . A method as recited in  claim 12 , wherein said connecting comprises: 
 disposing a first contact region in said device;    disposing a second contact region said element in a region of said second surface outside of a portion of said element covered by said device; and    forming said connection between said first and second contact regions.    
     
     
         15 . A method as recited in  claim 12 , wherein said connecting comprises: 
 exposing a first contact region in device through said first via;    exposing a second contact region in said element through said second via; and    forming said connection between said first and second contact regions.    
     
     
         16 . A method as recited in  claim 12 , comprising: 
 removing a portion of said substrate.    
     
     
         17 . A method as recited in  claim 12 , comprising: 
 removing substantially all of said first substrate.    
     
     
         18 . A method as recited in  claim 12 , comprising: 
 removing said first substrate after said bonding step.