US2008061419A1PendingUtilityA1

Three dimensional device integration method and integrated device

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Assignee: ZIPTRONIXPriority: Oct 1, 1999Filed: Oct 31, 2007Published: Mar 13, 2008
Est. expiryOct 1, 2019(expired)· nominal 20-yr term from priority
Inventors:Paul M. EnquistGaius Gillman Fountain, Jr.
H10W 99/00Y10S148/012Y10S438/977H10W 20/2134H10W 20/0234H10W 20/0242H10W 70/682H10W 90/297H10W 90/288H10W 90/722H10W 72/0198H10W 72/884H10W 90/756H10W 90/754H10W 72/50H10W 72/07551H10W 72/07554H10W 44/248H10W 70/093H10W 72/30H10W 72/07337H10W 72/07331H10W 72/073H10W 80/301H10W 80/327H10W 72/20H10W 72/07251H10W 90/00H10W 90/22H10W 70/60H10W 72/01225H10W 42/20H10W 70/614H10W 20/20H10W 40/10H10W 70/68H10W 20/023H10W 10/181H10P 72/7432H10P 72/7426H10P 72/743H10P 10/128H10P 90/1914H10P 72/74H10W 90/20H10W 80/732H10W 80/701H10W 72/07341H10W 72/07311H10W 72/01371H10W 72/01365H10W 72/01351H10W 72/357H10W 72/351H10W 72/347H10W 72/344H10W 72/337H10W 72/331H10W 90/401H10W 72/013H10W 70/635H10W 70/611H10D 88/00H10D 88/01H10D 84/038H10F 39/809
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Claims

Abstract

A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.

Claims

exact text as granted — not AI-modified
1 . An integration method, comprising: 
 bonding a first surface of a semiconductor device having a first substrate and an exposed peripheral side surface to an element having a second substrate with a second surface;    removing a portion of said first substrate to expose a third surface of said first semiconductor device; and    connecting said first semiconductor device and said element by forming a connection extending over said third surface, said peripheral side surface and said second surface.    
     
     
         2 . A method as recited in  claim 1 , wherein: 
 said first semiconductor device has a smaller area than an area of said element.    
     
     
         3 . A method as recited in  claim 2 , wherein said interconnecting comprises: 
 disposing a first contact region in said third surface;    disposing a second contact region in a region of said second surface outside of a portion of said second surface covered by said first semiconductor device; and    forming said connection between said first and second contact regions.    
     
     
         4 . A method as recited in  claim 1 , wherein said interconnecting comprises: 
 exposing a first contact region in said third surface;    exposing a second contact region in said second surface; and    forming said connection between said first and second contact regions.    
     
     
         5 . A method as recited in  claim 1 , wherein: 
 said removing comprises exposing in said third surface a first contact structure in said first device; and    said method comprises connecting said first contact structure to said element.    
     
     
         6 . A method as recited in  claim 5 , comprising: 
 exposing a second contact structure in said element; and    connecting said first contact structure to said second contact structure.    
     
     
         7 . A method as recited in  claim 1 , comprising: 
 removing substantially all of said first substrate.    
     
     
         8 . A method as recited in  claim 1 , comprising 
 forming a planarizing material over said second surface;    exposing a first contact structure in said first device;    forming a via in said material to expose a second contact structure in said element; and    forming said connection between said first and second contact structures through said via.    
     
     
         9 . A method as recited in  claim 1 , comprising: 
 removing said substrate after said bonding step.    
     
     
         10 . A method as recited in  claim 1 , comprising: 
 forming said connection in contact with said peripheral side surface.    
     
     
         11 . A method as recited in  claim 1 , comprising: 
 forming an insulative material on said peripheral side surface; and    forming said connection on said insulative material formed on said peripheral side surface.    
     
     
         12 . A method as recited in  claim 1 , comprising: 
 forming an insulative layer over said first semiconductor device and said element;    forming said connection over said insulative layer.    
     
     
         13 . A method as recited in  claim 1 , comprising: 
 forming an insulative layer over said first semiconductor device and said element;    forming holes in said insulative layer to expose a first contact structure in said device and a second contact structure in said element; and    forming said connection in contact with said first and second contact structures.    
     
     
         14 . A method as recited in  claim 1 , comprising: 
 forming a planarizing material over said device and said element;    forming first holes in said planarizing material to expose a first contact structure in said device and a second contact structure in said element;    forming an insulative layer over said planarixing material;    forming second holes in said insulative layer to expose said first and second contact structures; and    forming said connection in contact with said first and second contact structures.    
     
     
         15 . A method of integrating semiconductor devices, comprising: 
 bonding a first surface of a first semiconductor device, having a first substrate with a plurality of first semiconductor elements formed in a first insulative material and an exposed peripheral side surface of said first insulative material, to a second surface of a second semiconductor device;    removing said first substrate;    exposing a first contact structure in one of said first semiconductor elements;    exposing a second contact structure in said second device; and    connecting said first contact structure and second contact structure by forming a connection extending over said peripheral side surface.    
     
     
         16 . A method as recited in  claim 15 , wherein: 
 said first semiconductor device has a smaller area than an area of said second semiconductor device.    
     
     
         17 . A method as recited in  claim 15 , wherein said interconnecting comprises: 
 disposing said second contact structure in a region outside of a portion of said second surface covered by said first semiconductor device.    
     
     
         18 . A method as recited in  claim 15 , wherein: 
 said removing comprises exposing said first contact structure.    
     
     
         19 . A method as recited in  claim 15 , comprising 
 forming an insulative material over said second surface;    forming a via in said second insulative material to expose said second contact structure;    connecting said first and second contact structures through said via.    
     
     
         20 . A method as recited in  claim 15 , comprising: 
 connecting said first and second contact structures by forming a conductive material in contact with said peripheral side surface.    
     
     
         21 . A method as recited in  claim 15 , comprising: 
 removing said substrate after said bonding step.    
     
     
         22 . A method as recited in  claim 15 , comprising: 
 forming an insulative material on said peripheral side surface; and    connecting said first and second contact structures by forming a connection on said second insulative material formed on said peripheral side surface.    
     
     
         23 . A method as recited in  claim 15 , comprising: 
 forming an insulative layer over said first and second semiconductor devices;    forming said connection over said insulative layer.    
     
     
         24 . A method as recited in  claim 15 , comprising: 
 forming an insulative layer over said first and second semiconductor devices forming holes in said insulative layer to expose said first and second contact structures; and    forming said connection in contact with said first and second contact structures.    
     
     
         25 . A method as recited in  claim 15 , comprising: 
 forming a planarizing material over said device and said element;    forming first holes in said planarizing material to expose said first and second contact structures;    forming an insulative layer over said planarizing material;    forming second holes in said insulative layer to expose said first and second contact structures; and    forming said connection in contact with said first and second contact structures.    
     
     
         26 . An integrated structure, comprising: 
 a semiconductor device having a first substrate with a first and second opposing surfaces and an exposed peripheral side surface;    an element having a second substrate with a third surface, said third surface being bonded to said first surface;    a portion of said first substrate removed to expose a fourth surface of said first semiconductor device; and    a connection connecting said first semiconductor device and said element and extending over said third surface, said peripheral side surface and said second surface.    
     
     
         27 . A structure as recited in  claim 26 , comprising: 
 a first contact disposed in said device;    a second contact disposed in said element; and    said connection connecting said first and second contacts.    
     
     
         28 . A structure as recited in  claim 26 , comprising: 
 an insulating material formed on said first, third, fourth and peripheral side surfaces.    
     
     
         29 . A structure as recited in  claim 28 , comprising: 
 a via formed in said first substrate, wherein said insulating material is formed on side portions of said via.    
     
     
         30 . A structure as recited in  claim 26 , comprising: 
 a via formed in said first substrate, wherein said fourth surface comprises a portion of said via.

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