Semiconductor device

Abstract

A semiconductor integrated circuit device, such as a memory device or radiation detector, is disclosed, in which data storage cells are formed on a substrate. Each of the data storage cells includes a field effect transistor having a source, drain, and gate, and a body arranged between the source and drain for storing electrical charge generated in the body. The magnitude of the net electrical charge in the body can be adjusted by input signals applied to the transistor, and the adjustment of the net electrical charge by the input signals can be at least partially cancelled by applying electrical voltage signals between the gate and the drain and between the source and the drain.

1 . An integrated circuit device comprising: 
 a memory array, comprising: 
 a plurality of dynamic random access memory cells arranged in a matrix having a plurality of rows and columns, each dynamic random access memory cell comprises a transistor comprising: 
 a source region;  
 a drain region;  
 a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and  
 a gate spaced apart from the body region; and  
 
 wherein each memory cell includes three or more data states including: (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell, and (3) a third data state which corresponds to a third charge in the body region of the transistor of the memory cell.  
   
     
     
         2 . The integrated circuit device of  claim 1  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the amount of charge in the body region of the transistor associated with the given memory cell.  
     
     
         3 . The integrated circuit device of  claim 1  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the current output by the given memory cell in response to control signals applied to the transistor associated with the given memory cell.  
     
     
         4 . The integrated circuit device of  claim 1  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the current output by the transistor associated with the given memory cell.  
     
     
         5 . The integrated circuit device of  claim 1  further including means for reading the data state of the memory cells.  
     
     
         6 . The integrated circuit device of  claim 1  further including: 
 reading circuitry, coupled to the drain region of the transistor of each memory cell of a first row of dynamic random access memory cells, to determine the data state of each memory cell of a first plurality of dynamic random access memory cells;    control circuitry, coupled to gate of the transistor of each memory cell of the first plurality of dynamic random access memory cells, to provide control signals to each memory cell of the first plurality of dynamic random access memory cells; and    wherein, in response to a read control signal applied to the gate of the transistor of each memory cell of the first plurality of dynamic random access memory cells, the reading circuitry determines whether the memory cell is in a first data state, a second data state or a third data state based on the charge stored in the body region of the transistor of the memory cell.    
     
     
         7 . An integrated circuit device comprising: 
 a memory array, comprising: 
 a plurality of memory cells arranged in matrix having a plurality of rows and columns, each memory cell consists essentially of a transistor comprising: 
 a source region;  
 a drain region;  
 a body region disposed between the source region and the drain region, wherein the body region is electrically floating; and  
 a gate spaced apart from the body region; and  
 
 wherein each memory cell includes three or more data states including: (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell, and (3) a third data state which corresponds to a third charge in the body region of the transistor of the memory cell.  
   
     
     
         8 . The integrated circuit device of  claim 7  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the amount of charge in the body region of the transistor associated with the given memory cell.  
     
     
         9 . The integrated circuit device of  claim 7  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the current output by the given memory cell in response to control signals applied to the transistor associated with the given memory cell.  
     
     
         10 . The integrated circuit device of  claim 7  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the current output by the given memory cell.  
     
     
         11 . The integrated circuit device of  claim 7  further including means for reading the data state of the memory cells.  
     
     
         12 . The integrated circuit device of  claim 7  further including: 
 reading circuitry, coupled to the drain region of the transistor of each memory cell of a first row of dynamic random access memory cells, to determine the data state of each memory cell of a first plurality of dynamic random access memory cells;    control circuitry, coupled to gate of the transistor of each memory cell of the first plurality of dynamic random access memory cells, to provide control signals to each memory cell of the first plurality of dynamic random access memory cells; and    wherein, in response to a read control signal applied to the gate of the transistor of each memory cell of the first plurality of dynamic random access memory cells, the reading circuitry determines whether the memory cell is in a first data state, a second data state or a third data state based on the charge stored in the body region of the transistor of the memory cell.    
     
     
         13 . An integrated circuit device comprising 
 a memory array, disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the memory array comprising: 
 a plurality of memory cells disposed in or on the semiconductor region or layer, wherein each memory cell comprises a transistor comprising: 
 a source region having impurities to provide a first conductivity type;  
 a drain region having impurities to provide the first conductivity type,  
 a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type; and  
 a gate spaced apart from the body region; and  
 
 wherein each memory cell includes three or more data states including: (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell, and (3) a third data state which corresponds to a third charge in the body region of the transistor of the memory cell wherein at least one of the data states is at least partially provided by removing majority carriers from the body region through the source region of the transistor of the memory cell.  
   
     
     
         14 . The integrated circuit device of  claim 13  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the amount of charge in the body region of the transistor associated with the given memory cell.  
     
     
         15 . The integrated circuit device of  claim 13  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the current output by the given memory cell in response to control signals applied to the transistor associated with the given memory cell.  
     
     
         16 . The integrated circuit device of  claim 13  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the current output by the given memory cell.  
     
     
         17 . The integrated circuit device of  claim 13  further including means for reading the data state of the memory cells.  
     
     
         18 . The integrated circuit device of  claim 13  further including: 
 reading circuitry, coupled to the drain region of the transistor of each memory cell of a first row of dynamic random access memory cells, to determine the data state of each memory cell of a first plurality of dynamic random access memory cells;    control circuitry, coupled to gate of the transistor of each memory cell of the first plurality of dynamic random access memory cells, to provide control signals to each memory cell of the first plurality of dynamic random access memory cells; and    wherein, in response to a read control signal applied to the gate of the transistor of each memory cell of the first plurality of dynamic random access memory cells, the reading circuitry determines whether the memory cell is in a first data state, a second data state or a third data state based on the charge stored in the body region of the transistor of the memory cell.    
     
     
         19 . An integrated circuit device comprising 
 memory array, disposed in or on a semiconductor region or layer which resides on or above an insulating region or layer of a substrate, the memory array comprising: 
 a plurality of memory cells, arranged in a plurality of rows and columns and disposed in or on the semiconductor region or layer, wherein each memory cell consists essentially of a transistor comprising: 
 a source region having impurities to provide a first conductivity type;  
 a drain region having impurities to provide the first conductivity type,  
 a body region disposed between the source region, the drain region and the insulating region or layer of the substrate, wherein the body region is electrically floating and includes impurities to provide a second conductivity type wherein the second conductivity type is different from the first conductivity type; and  
 a gate spaced apart from the body region; and  
 
 wherein each memory cell includes three or more data states including: (1) a first data state which corresponds to a first charge in the body region of the transistor of the memory cell, (2) a second data state which corresponds to a second charge in the body region of the transistor of the memory cell, and (3) a third data state which corresponds to a third charge in the body region of the transistor of the memory cell.  
   
     
     
         20 . The integrated circuit device of  claim 19  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the amount of charge in the body region of the transistor of the given memory cell.  
     
     
         21 . The integrated circuit device of  claim 19  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the current output by the given memory cell in response to control signals applied to the transistor associated with the given memory cell.  
     
     
         22 . The integrated circuit device of  claim 19  further including read circuitry, coupled to the memory cells, to read the data state of the memory cell, wherein the read circuitry determines the data state of a given memory cell based on the current output by the given memory cell.  
     
     
         23 . The integrated circuit device of  claim 19  further including means for reading the data state of the memory cells.  
     
     
         24 . The integrated circuit device of  claim 19  wherein at least one of the data states is substantially provided by removing majority carriers from the body region through the source region of the transistor of the memory cell.  
     
     
         25 . The integrated circuit device of  claim 19  further including: 
 reading circuitry, coupled to the drain region of the transistor of each memory cell of a first row of dynamic random access memory cells, to determine the data state of each memory cell of a first plurality of dynamic random access memory cells;    control circuitry, coupled to gate of the transistor of each memory cell of the first plurality of dynamic random access memory cells, to provide control signals to each memory cell of the first plurality of dynamic random access memory cells; and    wherein, in response to a read control signal applied to the gate of the transistor of each memory cell of the first plurality of dynamic random access memory cells, the reading circuitry determines whether the memory cell is in a first data state, a second data state or a third data state based on the charge stored in the body region of the transistor of the memory cell.