Method of manufacturing a nonvolatile semiconductor memory device and select gate device having a stacked gate structure

Abstract

A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells. The select gate is formed with a STI recess process in advance locally in the select area.

1 . A non-volatile semiconductor device structure comprising: 
 a semiconductor substrate;    a plurality of element-forming regions partitioned by element isolation/insulation films in said semiconductor substrate;    floating gates formed in said element-forming regions via a first gate insulating film and separated for individual said element-forming regions;    Second gate insulating films formed on said floating gates, and divided and separated above said element isolation/insulation films;    Control gates formed on said floating gates via said second gate insulating films; and source and drain diffusion layers formed in self-alignment with said control gates.    
   
   
       2 . The method according to  claim 1 , wherein the floating gate is divided and separated by increasing the height of element insulation films ( 301 ), followed by first gate formed in said element-forming region via a first gate insulating film, and followed by a CMP (Chemical Mechanical Polish) process to divide and separate the floating gates.  
   
   
       3 . The method according to  claim 2 , wherein the division and separation of floating gates is processed by floating gate material etch back process.  
   
   
       4 . The method according to  claim 2 , wherein the height of element insulation films ( 301 ) is increased for the division and separation of floating gates during CMP or floating gate material etch back process.  
   
   
       5 . The method according to  claim 2 , wherein the height of element insulation films ( 301 ) is increased by increasing the thickness of STI pad nitride  800 , or reducing the oxide loss after STI pad nitride removal  
   
   
       6 . A semiconductor device structure for select gate comprising: 
 forming a first layer of polysilicon over a tunnel oxide layer, said tunnel oxide layer being situated on a substrate; the first layer of polysilicon is not patterned during the division and separation of floating gates;    fabricating an ONO stack and 2nd layer of polysilicon over said first layer of polysilicon; the 2nd layer of polysilicon can either be electrically connected to 1st layer of polisilicon or not.    
   
   
       7 . The method according to  claim 6  wherein said the 1st polysilicon in select gate area is protected during the process of division and separation of floating gates.  
   
   
       8 . The method according to  claim 7 , wherein the height of element insulation films ( 301 ) in the select gate area is intentionally reduced before the formation of a first gate insulating film.  
   
   
       9 . The method according to  claim 8 , wherein the reduction of the height of element insulation films ( 301 ) can be either by wet etch process or dry etch process  
   
   
       10 . The method according to  claim 2  and  claim 7 , wherein the height of element insulation films in non-volatile semiconductor device area is protected during the reduction of the height of element insulation films ( 301 ) in the select gate area.  
   
   
       11 . The method according to  claim 10 , wherein the height of element insulation films in non-volatile semiconductor device area can be protected by photoresist, while the select gate area is exposed to the etch process