Dual Independent and Shared Resource Vector Execution Units With Shared Register File

Abstract

The present invention is generally related to the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.

1 . A processor comprising:
 a first vector unit; and   a second vector unit,   wherein the first vector unit and the second vector unit each comprise a plurality of vector processing lanes configured to execute a vector instruction and at least one scalar processing lane configured to execute a scalar instruction, the first vector unit and the second vector unit being configured to independently and simultaneously execute instructions.   
   
   
       2 . The processor of  claim 1 , wherein first vector unit and the second vector unit are configured to execute a single instruction. 
   
   
       3 . The processor of  claim 2 , wherein the instruction is configured to determine a cross product of two vectors. 
   
   
       4 . The processor of  claim 1 , further comprising a register file comprising a plurality of registers, the plurality of registers being configured to store vector and scalar data. 
   
   
       5 . The processor of  claim 4 , wherein the first vector unit and the second vector unit are communicably coupled with the register file and configured to receive data from a plurality of registers in the register file. 
   
   
       6 . The processor of  claim 4 , wherein each of the first vector unit and the second vector unit comprise a write back path configured to write back results from the vector units to the register file. 
   
   
       7 . The processor of  claim 1 , wherein the plurality of vector processing lanes of each vector unit are configured to perform a plurality of operations in parallel on a plurality of vector operands, the plurality of operations being determined by a single vector instruction. 
   
   
       8 . The processor of  claim 6 , wherein each vector processing lane comprises one or more functional units, each functional unit being configured to perform an operation from the plurality of operations. 
   
   
       9 . The processor of  claim 8 , wherein the functional units comprise multipliers, aligners, and adders. 
   
   
       10 . A method for processing instructions, comprising:
 issuing a first instruction to a first vector unit; and   simultaneously issuing a second instruction to a second vector unit,   wherein the first vector unit and the second vector unit are configured to independently and simultaneously process the first instruction and the second instruction.   
   
   
       11 . The method of  claim 10 , further comprising, issuing a third instruction to the first vector unit and the second vector unit, wherein the first vector unit and the second vector unit are configured to process the instruction. 
   
   
       12 . The method of  claim 11 , wherein the third instruction determines a cross product between two vectors. 
   
   
       13 . The method of  claim 10 , wherein the first vector unit and the second vector unit comprise a plurality of vector processing lanes and at least one scalar processing lane. 
   
   
       14 . The method of  claim 13 , wherein the first instruction is a vector instruction. 
   
   
       15 . The method of  claim 14 , wherein processing the first instruction comprises processing the first instruction in the plurality of vector processing lanes, the processing comprising performing a plurality of operations in parallel on a plurality of vector operands, the plurality of operations being determined by the first instruction. 
   
   
       16 . A system, comprising a plurality of processors communicably coupled with one another, wherein each processor comprises:
 a first vector unit; and   a second vector unit,   wherein the first vector unit and the second vector unit each comprise a plurality of vector processing lanes configured to execute a vector instruction and at least one scalar processing lane configured to execute a scalar instruction, the first vector unit and the second vector unit being configured to independently and simultaneously execute instructions.   
   
   
       17 . The system of  claim 16 , wherein first vector unit and the second vector unit are configured to execute a single instruction. 
   
   
       18 . The system of  claim 17 , wherein the instruction is configured to determine a cross product of two vectors. 
   
   
       19 . The system of  claim 16 , further comprising a register file comprising a plurality of registers, the plurality of registers being configured to store vector and scalar data. 
   
   
       20 . The system of  claim 19 , wherein the first vector unit and the second vector unit are communicably coupled with the register file and configured to receive data from a plurality of registers in the register file. 
   
   
       21 . The system of  claim 19 , wherein each of the first vector unit and the second vector unit comprise a write back path configured to write back results from the vector units to the register file. 
   
   
       22 . The system of  claim 16 , wherein the plurality of vector processing lanes of each vector unit are configured to perform a plurality of operations in parallel on a plurality of vector operands, the plurality of operations being determined by a single vector instruction. 
   
   
       23 . The system of  claim 22 , wherein each vector processing lane comprises one or more functional units, each functional unit being configured to perform an operation from the plurality of operations. 
   
   
       24 . The system of  claim 23 , wherein the functional units comprise multipliers, aligners, and adders.