Fabrication Process For Increased Capacitance In An Embedded DRAM Memory

Abstract

An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.

1 . An embedded dynamic random access memory (DRAM) system comprising: 
 a semiconductor substrate having a first conductivity type;    a first set of trench isolation regions having a first depth below an upper surface of the semiconductor substrate, the first set of trench isolation regions being located in a first area of the semiconductor substrate;    a second set of trench isolation regions having a second depth, greater than the first depth, below an upper surface of the semiconductor substrate, the second set of trench isolation regions being located in a second area of the semiconductor substrate;    a plurality of logic transistors fabricated in the first area of the semiconductor substrate, wherein the logic transistors are isolated by the first set of trench isolation regions; and    a plurality of dynamic random access memory (DRAM) cells fabricated in the second area of the semiconductor substrate, wherein the DRAM cells are isolated by the second set of trench isolation regions.    
     
     
         2 . The embedded DRAM system of  claim 1 , wherein the second depth is greater than the first depth by at least about 20 percent.  
     
     
         3 . The embedded DRAM system of  claim 1 , wherein each of the DRAM cells comprises a cell capacitor having a capacitor electrode located at least partially in one of the second set of trench isolation regions.  
     
     
         4 . The embedded DRAM system of  claim 3 , wherein the cell capacitor further includes a dielectric layer located on a sidewall of one of the second set of trenches.  
     
     
         5 . The embedded DRAM system of  claim 3 , wherein the cell capacitor further includes an inversion layer located in the sidewall of one of the second set of trenches.  
     
     
         6 . The embedded DRAM system of  claim 1 , wherein the DRAM cells include access transistors having a first gate dielectric layer and cell capacitors having a capacitor dielectric layer, and wherein the logic transistors have a second gate dielectric layer, wherein the capacitor dielectric layer, the first gate dielectric layer and the second gate dielectric layer are the same layer.  
     
     
         7 . The embedded DRAM system of  claim 1 , wherein the DRAM cells include access transistors having a first gate dielectric layer and cell capacitors having a capacitor dielectric layer, and wherein the logic transistors have a second gate dielectric layer, wherein the capacitor dielectric layer and the first gate dielectric layer have a different thickness or composition than the second gate dielectric layer.  
     
     
         8 . The embedded DRAM system of  claim 7 , wherein the capacitor dielectric layer and the first gate dielectric layer are the same layer.  
     
     
         9 . The embedded DRAM system of  claim 7 , wherein the capacitor dielectric layer and the first gate dielectric layer have different compositions and or thicknesses.  
     
     
         10 . The embedded DRAM system of  claim 1 , wherein the DRAM cells include access transistors having a first gate dielectric layer and cell capacitors having a capacitor dielectric layer, wherein the capacitor dielectric layer and the first gate dielectric layer have different thicknesses or compositions.  
     
     
         11 . The embedded DRAM system of  claim 3 , wherein each of the DRAM cells further includes an access transistor having a gate electrode, a first source/drain region coupled to the cell capacitor and a second source/drain region.  
     
     
         12 . The embedded DRAM system of  claim 11 , wherein the second source/drain region has a higher dopant concentration than the first source/drain region.  
     
     
         13 . The embedded DRAM system of  claim 11 , further comprising metal silicide located over the gate electrode and the second source/drain region.  
     
     
         14 . The embedded DRAM system of  claim 13 , wherein the first source/drain region is substantially free of metal silicide.  
     
     
         15 . The embedded DRAM system of  claim 13 , wherein the capacitor electrode is substantially free of metal silicide.  
     
     
         16 . The embedded DRAM system of  claim 11 , wherein the gate electrode and the capacitor electrode comprise polycrystalline silicon.  
     
     
         17 . The embedded DRAM system of  claim 16 , wherein the gate electrode and the capacitor electrode are fabricated from the same layer of polycrystalline silicon.  
     
     
         18 . The embedded DRAM system of  claim 11 , wherein gate electrodes of the logic transistors, the gate electrodes of the access transistors and the capacitor electrodes are fabricated from the same layer of polycrystalline silicon.