Polysilicon levels for silicided structures including MOSFET gate electrodes and 3D devices

Abstract

Semiconductor structures having a silicided gate electrode and methods of manufacture are provided. A device comprises a first silicided structure formed in a first active region and a second silicided structure formed in a second active region. The two silicided structures have different metal concentrations. A method of forming a silicided device comprises forming a polysilicon structure on the first and second device fabrication regions. Embodiments include replacing a first portion of the polysilicon structure on the first device fabrication region with a metal and replacing a second portion of the polysilicon structure on the second device fabrication region with the metal. Preferably, the second portion is different than the first portion. Embodiments further include reacting the polysilicon structures on the first and second device fabrication regions with the metal to form a silicide.

1 . A semiconductor device comprising:
 a semiconductor substrate comprising a first active region and a second active region; a first silicided structure formed in the first active region, wherein the first silicided structure has a first metal concentration; and   a second silicided structure formed in the second active region, wherein the second silicided structure has a second metal concentration, the second metal concentration not equal to the first metal concentration.   
   
   
       2 . The semiconductor chip of  claim 1 , wherein the first and second silicided structures each comprise a transistor gate electrode of a transistor. 
   
   
       3 . The semiconductor chip of  claim 2 , wherein the transistor further comprises a gate dielectric selected from the group consisting essentially of SiO2, SiON, HfSiON, Ta2O5, TiO2, Al2O3, ZrO2, HfO2, Y2O3, La2O3, HfSiOX, HfAlOX, PbTiO3, BaTiO3, SrTiO3, PbZOr3, aluminates and silicates thereof, and combinations thereof. 
   
   
       4 . The semiconductor device of  claim 1 , wherein the first and second active regions are separated by an isolation structure. 
   
   
       5 . The semiconductor device of  claim 1 , wherein the first and second silicided structures each comprise a silicide of a material selected from the group consisting essentially of Ni, Co, Cu, Mo, Ti, Ta, W, Er, Zr, Pt, Yb, Hf, Al, Zn and combinations thereof. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the substrate comprises a semiconductor substrate selected from the group consisting essentially of silicon, germanium, silicon germanium, and silicon-on-insulator. 
   
   
       7 . The semiconductor device of  claim 1 , further comprising a dielectric layer overlying the first and second silicided structures. 
   
   
       8 . A semiconductor device comprising:
 an isolation region formed in a substrate, wherein the isolation region electrically isolates a first active region and a second active region;   a first transistor formed in the first active region, the first transistor comprising a first fully silicided gate electrode; and   a second transistor formed in the second active region, the second transistor comprising a second fully silicided gate electrode, wherein the height of the second gate electrode not equal to the height of the first gate electrode.   
   
   
       9 . The semiconductor device of  claim 8 , wherein the first fully silicided gate electrode and the second silicided gate electrode each comprise a silicide of a material selected from the group consisting essentially of Ni, Co, Cu, Mo, Ti, Ta, W, Er, Zr, Pt, Yb, Hf, Al, Zn, and combinations thereof. 
   
   
       10 . The semiconductor device of  claim 8 , wherein an atomic ratio of metal to silicon in the first fully silicided gate electrode is greater than about 0.6. 
   
   
       11 . The semiconductor device of  claim 8 , wherein an atomic ratio of metal to silicon in the second silicided gate electrode is less than about 0.6. 
   
   
       12 . The method of  claim 8 , wherein a height of the silicided gate electrodes is substantially the same. 
   
   
       13 . The semiconductor chip of  claim 8 , wherein the first and second transistors further comprise a gate dielectric material selected from the group consisting essentially of SiO2, SiON, HfSiON, Ta2O5, TiO2, Al2O3, ZrO2, HfO2, Y2O3, La2O3, HfSiOx, HfAlOx, PbTiO3, BaTiO3, SrTiO3, PbZrO3, aluminates and silicates thereof, and combinations thereof. 
   
   
       14 . The semiconductor device of  claim 8 , wherein the first and second transistors are separated by an isolation structure. 
   
   
       15 . The semiconductor device of  claim 8 , wherein the substrate comprises a semiconductor substrate selected from the group consisting essentially of silicon, germanium, silicon germanium, SiC, III-V compounds, and silicon-on-insulator. 
   
   
       16 . A semiconductor device comprising:
 a substrate;   a first transistor having a first fully silicided gate overlying the substrate and having a first height; and   a second transistor having a second fully silicided gate overlying the substrate and having a second height, the height ratio of the first height to the second height being not larger than ½.   
   
   
       17 . The semiconductor device of  claim 16  wherein said first fully silicided gate comprises nickel silicide. 
   
   
       18 . The semiconductor device of  claim 16  wherein said first transistor is an NFET. 
   
   
       19 . The semiconductor device of  claim 16  wherein:
 said first transistor includes;   a first source region;   a first drain region;   a first channel region between the first source region and first drain region;   a first gate dielectric overlying the first channel region; and   said second transistor includes;   a second source region;   a second drain region;   a second channel region between the second source region and second drain region;   a second gate dielectric overlying the second channel region.   
   
   
       20 . The semiconductor device of  claim 16  wherein said first transistor and said second transistor are electrically connected in a CMOS configuration.