Three dimensional device integration method and integrated device
Abstract
A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed. A conductor array having a plurality of contact structures may be formed on an exposed surface of the semiconductor device, vias may be formed through the semiconductor device to device regions, and interconnection may be formed between said device regions and said contact structures.
Claims
exact text as granted — not AI-modified1 . An integration method, comprising:
forming first and second bonding surfaces on first and second materials each having a surface roughness of less than about 1 nm; directly bonding said first element to said second element without fusing said first element to said second element; and removing a substantial portion of said first material to leave a remaining portion; forming a third bonding surface on said remaining portion having a surface roughness of less than about 1 nm; directly bonding said first element to a third element without fusing said first element to said second element; and removing said second element.
2 . A method as recited in claim 1 , wherein:
said first element has a smaller area than an area of said second element.
3 . A method as recited in claim 1 , comprising
forming an electrical connection between said first and third element.
4 . A method as recited in claim 1 , wherein said third element comprises silicon;
5 . A method as recited in claim 1 , wherein a surface of said third element bonded to said remaining portion comprises silicon.
6 . A bonded structure, comprising:
first and second elements having first and second bonding surfaces, respectively, at least one of said surfaces comprising an insulating material; said first and second materials directly bonded through direct contact of said first and second surfaces without fusing said first element to said second element; a top portion of said first material being removed to expose a contact structure; a second contact structure disposed in said second element; and an electrical connection formed between first and second contact structures extending over said top portion.
7 . A structure as recited in claim 6 , wherein:
said second material comprises silicon.
8 . A structure as recited in claim 6 , wherein said insulating material comprises silicon oxide.Join the waitlist — get patent alerts
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