US2008098268A1PendingUtilityA1

Using clock gating or signal gating to partition a device for fault isolation and diagnostic data collection

Assignee: IBMPriority: Aug 15, 2001Filed: Oct 31, 2007Published: Apr 24, 2008
Est. expiryAug 15, 2021(expired)· nominal 20-yr term from priority
G01R 31/31937G01R 31/31922G01R 31/318594G01R 31/31725
45
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

In one aspect, an electronic device that has been partitioned into segments by using clock gating or signal gating is tested. One of the segments that is a source of a failure is identified. Diagnostic procedures are applied to the identified segment to determine a cause of the failure.

Claims

exact text as granted — not AI-modified
1 . A test control device adapted to: 
 couple to an electronic device that is adapted to be partitioned into segments by using clock gating or signal gating; and    control the electronic device to identify one of the segments that is a source of a failure by selectively disabling at least one of the segments.    
   
   
       2 . A computer system chip comprising: 
 a test control device adapted to: 
 couple to an electronic device to be tested;  
 partition the electronic device into a plurality of segments by using clock gating or signal gating; and  
 control the electronic device to identify one of the plurality of segments that is a source of a failure by selectively disabling at least one of the plurality of segments.  
   
   
   
       3 . The computer system chip of  claim 2  wherein the test control device is adapted to partition the electronic device into the plurality of segments by using clock gating.  
   
   
       4 . The computer system chip of  claim 2  wherein the test control device is adapted to partition the electronic device into the plurality of segments by using signal gating.  
   
   
       5 . A testing arrangement comprising: 
 a test control device adapted to: 
 couple to an electronic device that is adapted to be partitioned into segments by using clock gating or signal gating; and  
 control the electronic device to identify one of the segments that is a source of a failure by selectively disabling at least one of the segments; and  
   a computer adapted to employ the test control device to: 
 partition the electronic device into segments by using clock gating or signal gating; and  
 identify one of the segments that is a source of a failure by selectively disabling at least one of the segments.

Join the waitlist — get patent alerts

Track US2008098268A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.