Carbon filament memory and method for fabrication

Abstract

A nonvolatile memory cell is described, including a carbon layer system that includes an sp 2 -rich amorphous carbon layer and an sp 3 -rich amorphous carbon layer, wherein information is stored in the nonvolatile memory cell by reversibly forming an sp 2 -rich filament in the sp 3 -rich amorphous carbon layer.

1 . A nonvolatile memory cell comprising:
 a carbon layer system that includes an sp 2 -rich amorphous carbon layer and an sp 3 -rich amorphous carbon layer,   wherein information can be stored in the nonvolatile memory cell by reversibly forming an sp 2 -rich filament in the sp 3 -rich amorphous carbon layer.   
     
     
         2 . The nonvolatile memory cell of  claim 1 , wherein the sp 2 -rich filament changes a conductivity of the carbon layer system. 
     
     
         3 . The nonvolatile memory cell of  claim 1 , wherein the sp 3 -rich amorphous carbon layer has a thickness of 5 nm or less. 
     
     
         4 . The nonvolatile memory cell of  claim 1 , further comprising a select transistor coupled to the carbon layer system. 
     
     
         5 . The nonvolatile memory cell of  claim 1 , wherein the carbon layer system stores multiple bits of information. 
     
     
         6 . The nonvolatile memory cell of  claim 5 , wherein different resistance states of the carbon layer system are used to store the multiple bits of information. 
     
     
         7 . The nonvolatile memory cell of  claim 1 , wherein application of a first current through the carbon layer system causes growth of the sp 2 -rich filament. 
     
     
         8 . The nonvolatile memory cell of  claim 7 , wherein application of a second current, having a reversed polarity with respect to the first current, causes reduction of the sp 2 -rich filament. 
     
     
         9 . The nonvolatile memory cell of  claim 1 , wherein the carbon layer system comprises a carbon bi-layer system. 
     
     
         10 . An information storage element, comprising:
 a first carbon layer comprising an amorphous carbon film including sp 2  hybridized carbon and sp 3  hybridized carbon, the first carbon layer having a higher proportion of sp 2  hybridized carbon than sp hybridized carbon; and   a second carbon layer disposed adjacent to the first carbon layer, the second carbon layer comprising an amorphous carbon film including sp 2  hybridized carbon and sp 3  hybridized carbon, the second carbon layer having a higher proportion of sp 3  hybridized carbon than sp 2  hybridized carbon,   wherein information is stored by forcing a first current through the first carbon layer and the second carbon layer to cause growth of a filament in the second carbon layer, the filament having a substantially higher proportion of sp 2  hybridized carbon than sp 3  hybridized carbon.   
     
     
         11 . The information storage element of  claim 10 , wherein the filament is reduced by forcing a second current, having a reversed polarity with respect to the first current, through the first carbon layer and the second carbon layer. 
     
     
         12 . The information storage element of  claim 10 , wherein the first carbon layer has a resistance R 1 , the second carbon layer has a resistance R 2 , and wherein a ratio R 2 /R 1  is greater than 100 when the filament is absent. 
     
     
         13 . The information storage element of  claim 10 , wherein growth of the filament increases a conductivity of the information storage element. 
     
     
         14 . The information storage element of  claim 10 , wherein the second carbon layer has a thickness of 5 nm or less. 
     
     
         15 . The information storage element of  claim 10 , wherein different resistance states of the information storage element are used to store multiple bits of information in the information storage element. 
     
     
         16 . A nonvolatile memory cell comprising:
 a transistor; and   a carbon layer system, comprising a first carbon layer, having a first resistance R 1 , and a second carbon layer, having a second resistance R 2 , such a ratio R 2 /R 1  is greater than 100,   wherein one of the layers of the carbon layer system is connected to a drain portion of the transistor.   
     
     
         17 . A method for storing information, comprising:
 providing a carbon layer system that includes an sp 2 -rich amorphous carbon layer and an sp 3 -rich amorphous carbon layer; and   reversibly forming an sp 2 -rich filament in the sp 3 -rich amorphous carbon layer to store the information.   
     
     
         18 . The method of  claim 17 , wherein reversibly forming the sp 2 -rich filament comprises applying a first current through the carbon layer system to cause growth of the sp 2 -rich filament. 
     
     
         19 . The method of  claim 18 , wherein reversibly forming the sp 2 -rich filament further comprises applying a second current, having a reversed polarity with respect to the first current, to cause reduction of the sp 2 -rich filament. 
     
     
         20 . The method of  claim 17 , wherein reversibly forming the sp 2 -rich filament comprises changing a resistance of the carbon layer system. 
     
     
         21 . The method of  claim 20 , wherein changing the resistance of the carbon layer system comprises changing the resistance in steps. 
     
     
         22 . The method of  claim 21 , wherein changing the resistance in steps further comprises using different steps to represent multiple bits of information. 
     
     
         23 . A method of fabricating a nonvolatile memory device, comprising:
 depositing a first carbon layer comprising an amorphous carbon film including sp 2  hybridized carbon and sp hybridized carbon, the first carbon layer having a higher proportion of sp 2  hybridized carbon than sp 3  hybridized carbon;   depositing a second carbon layer adjacent to the first carbon layer, the second carbon layer comprising an amorphous carbon film including sp 2  hybridized carbon and sp 3  hybridized carbon, the second carbon layer having a higher proportion of sp 3  hybridized carbon than sp 2  hybridized carbon; and   forming contacts that permit a current to be selectively applied through the first carbon layer and second carbon layer.   
     
     
         24 . The method of  claim 23 , further comprising forming a transistor having a drain region that is coupled to at least one of the contacts to selectively apply current through the first carbon layer and second carbon layer. 
     
     
         25 . A method of fabricating a nonvolatile memory device, comprising depositing on a semiconductor wafer a carbon layer system comprising a first carbon layer, having a first resistance R 1 , and a second carbon layer, having a second resistance R 2 , such that a ratio R 2 /R 1  is greater than 100. 
     
     
         26 . A computing system comprising:
 an input device;   an output device;   a processor coupled to the input device and the output device; and   a nonvolatile memory coupled to the processor, said nonvolatile memory comprising a carbon layer system that includes an sp 2 -rich amorphous carbon layer and an sp 3 -rich amorphous carbon layer, wherein information is stored in the nonvolatile memory by reversibly forming an sp 2 -rich filament in the sp 3 -rich amorphous carbon layer.   
     
     
         27 . The computing system of  claim 26 , wherein the output device comprises a wireless communications device.