Method of manufacturing semiconductor device

Abstract

There is provided a dry etching method for forming wiring trenches in a first insulating layer and in a second insulating layer provided thereon. First, the second insulating layer is etched partway under first etching conditions using resist as a mask (first etching step). Next, the remnant of the second insulating layer and the first insulating layer are etched under second etching conditions different from the first etching conditions, without changing the etching conditions (second etching step).

1 . A method of manufacturing a semiconductor device having a first insulating layer and a second insulating layer provided thereon, comprising:
 etching said second insulating layer without exposing said first insulating layer under first etching condition; and   etching remnant of said second insulating layer left over said first insulating layer and said first insulating layer under second etching condition different from the first etching condition.   
     
     
         2 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein said second etching condition has not etching selectivity to said first and second insulating layer. 
     
     
         3 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein an etching time in said first etching step is no shorter than 60% but no longer than 90% of an etching time required to etch said second insulating layer to the last. 
     
     
         4 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the thickness of said remnant of said second insulating layer is no less than 10% but no greater than 40% of the total thickness of said second insulating layer. 
     
     
         5 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein the flow rate of oxygen is larger under said second etching conditions than under said first etching conditions. 
     
     
         6 . The method of manufacturing a semiconductor device as claimed in  claim 5 , wherein the mixing ratio of oxygen in said second etching conditions is no lower than 0.4% but no higher than 2.6%. 
     
     
         7 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein top power is higher under said second etching conditions than under said first etching conditions. 
     
     
         8 . The method of manufacturing a semiconductor device as claimed in  claim 7 , wherein said top power under said second etching conditions is no lower than 1300 W but no higher than 2200 W. 
     
     
         9 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein said second insulating layer has permittivity higher than that of said first insulating layer. 
     
     
         10 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein said first insulating layer is a low-k dielectric layer. 
     
     
         11 . The method of manufacturing a semiconductor device as claimed in  claim 10 , wherein said first insulating layer is made of SiOC. 
     
     
         12 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein said second insulating layer is made of SiO 2 , SiC, SiCN, SiN or BCB. 
     
     
         13 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein no etch stop layer is interposed between said first and second insulating layers. 
     
     
         14 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein said first and second etching steps are carried out as part of a dual damascene process. 
     
     
         15 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein
 a gas consisting primarily of CH4-nFn (“n” is a natural number equal to or smaller than 4) is used with a pressure being no lower than 30 mTorr but no higher than 60 mTorr,   top power being no lower than 200 W but no higher than 600 W,   bias output thereof being no lower than 700 W but no higher than 1300 W, and   flow rate of Ar being no lower than 0.91/min (900 sccm) but no higher than 1.81/min (1800 sccm) under said first condition.   
     
     
         16 . The method of manufacturing a semiconductor device as claimed in  claim 1 , wherein
 a gas consisting primarily of CH4-nFn (“n” is a natural number equal to or smaller than 4) is used with a pressure being no lower than 30 mTorr but no higher than 60 mTorr,   top power being no lower than 1300 W but no higher than 2200 W,   bias output thereof being no lower than 600 W but no higher than 1200 W, and   flow rate of Ar being no lower than 0.21/min (200 sccm) but no higher than 0.61/min (600 sccm) under said second condition.   
     
     
         17 . A method of a semiconductor devices comprising:
 forming a first insulating layer and a second insulating layer on the first insulating layer;   performing an etching process in a first condition to make a hole in the second insulating layer, the hole having a depth that is smaller than a thickness of the second insulating layer so that a portion of the second insulating layer intervening between the first hole and the first insulating layer; and   performing an etching process in a second condition to remove the portion of the second insulating layer and make a second hole in the first insulating layer, the second condition being different from the first condition.   
     
     
         18 . The method as claimed in  claim 17 , wherein the first and second holes are substantial equal in size to each other. 
     
     
         19 . The method as claimed in  claim 17 , wherein the first and second insulating layer s are different in a material from each other.