Semiconductor chip having bumps of different heights and semiconductor package including the same

Abstract

A semiconductor chip is disclosed and includes a plurality of bond pads disposed on a semiconductor chip, and a plurality of chip bumps of different heights disposed on a corresponding bond pad.

1 . A semiconductor chip comprising:
 a plurality of bond pads disposed on a semiconductor chip; and   a plurality of chip bumps of different heights disposed on a corresponding bond pad.   
     
     
         2 . The semiconductor chip of  claim 1 , wherein the plurality of bond pads are arranged in a plurality of rows on the semiconductor chip. 
     
     
         3 . The semiconductor chip of  claim 2 , wherein each one of the plurality of chip bumps varies in respective height according to the row of its corresponding bond pad. 
     
     
         4 . The semiconductor chip of  claim 3 , wherein adjacent rows in the plurality of bond pad rows are arranged with an offset. 
     
     
         5 . The semiconductor chip of  claim 4 , wherein the plurality of bond pad rows are arranged in a zigzag pattern and are connected to a collection of inner leads arranged in a staggered offset pattern. 
     
     
         6 . The semiconductor chip of  claim 1 , wherein the plurality of bond pads are arranged in a first row, a second row, and third row on the semiconductor chip; and
 the plurality of chip bumps comprises;
 first chip bumps having a first height and being respectively connected to a bond pad in the first row of bond pads; 
 second chip bumps having a second height greater than the first height and being respectively connected to a bond pad in the second row of bond pads; 
 third chip bumps having a third height greater than the second height and being respectively connected to a bond pad in the third row of bond pads. 
   
     
     
         7 . The semiconductor chip of  claim 6 , wherein the first height for the first chip bumps is zero. 
     
     
         8 . The semiconductor chip of  claim 6 , further comprising a chip mounting area receiving a collection of inner leads;
 wherein the first, second, and third bond pad rows are arranged in an adjacent row offset pattern beginning with the first bond pad row disposed proximate an edge of the chip mounting area, the second bond pad row disposed behind the first bond pad row further away from the edge of the chip mounting area, and the third bond pad row disposed behind the second bond pad row still further away from the edge of the chip mounting area.   
     
     
         9 . The semiconductor chip of  claim 6 , wherein at least the second and third chip bumps respectively terminate in an irregularly shaped end portion. 
     
     
         10 . A semiconductor package comprising:
 a plurality of chip bumps connected to corresponding bond pads on a semiconductor chip, wherein the plurality of chip bumps includes first chip bumps having a first height and second chip bumps having a second height greater than the first height;   a circuit board comprising a plurality of first inner leads each having a first lead bump of first height, and a plurality of second inner leads each having a second lead bump of second height less than the first height;   wherein electrical connection of the semiconductor chip and the circuit board is made through respective combinations of a first chip bump and a first lead bump and a second chip bump and a second lead bump.   
     
     
         11 . The semiconductor package of  claim 10 , wherein the semiconductor package is one selected from the group consisting of a chip on film (COF) and a tape carrier package (TCP). 
     
     
         12 . The semiconductor package of  claim 10 , wherein the semiconductor package is a flip chip package. 
     
     
         13 . The semiconductor package of  claim 10 , wherein the bond pads of the semiconductor chip are formed in a plurality of rows. 
     
     
         14 . The semiconductor package of  claim 13 , wherein each first chip bump is respectively connected to a bond pad in a first row of bond pads and each second chip bump is respectively connected to a bond pad in a second row of bond pads. 
     
     
         15 . The semiconductor package of  claim 10 , wherein each lead bump extends from an inner lead in an angular manner to terminate in an end portion wider than a portion connecting the inner lead, and each chip bump extends from a bond pad in an angular manner to terminate in an end portion wider than a portion connecting the bond pad. 
     
     
         16 . The semiconductor package of  claim 10 , wherein each lead bump extends from an inner lead in an angular manner to terminate in an end portion narrower than a portion connecting the inner lead, and each chip bump extends from a bond pad in an angular manner to terminate in an end portion narrower than a portion connecting the bond pad. 
     
     
         17 . The semiconductor package of  claim 10 , wherein each lead bump comprises; a nickel (Ni) layer formed between an inner lead formed from copper (Cu), and a gold (Au) layer formed on the Ni layer. 
     
     
         18 . The semiconductor package of  claim 10 , wherein the bond pads of the semiconductor chip are arranged in first, second and third rows;
 the plurality of chip bumps further comprises third chip bumps having a third height greater than the second height and the circuit board further comprises a plurality of third inner leads each having a third lead bump of third height greater than the second height; and   electrical connection of the semiconductor chip and the circuit board is additionally made through respective combinations of a third chip bump and a third lead bump.   
     
     
         19 . The semiconductor package of  claim 18 , wherein each first lead bump makes connection to a corresponding first chip bump associated with a bond pad in the first row of bond pads;
 each second lead bump makes connection to a corresponding second chip bump associated with a bond pad in the second row of bond pads; and   each third lead bump makes connection to a corresponding third chip bump associated with a bond pad in the third row of bond pads.   
     
     
         20 . The semiconductor package of  claim 19 , wherein at least each second and third chip bump and each first and second lead bump terminates in an irregular end portion.