Method of manufacturing a multi-layer wiring board using a metal member having a rough surface

Abstract

Methods are provided for manufacturing a wiring circuit element or wiring board in which a set of rough wiring patterns are formed by selectively etching a metal layer of a patternable member which includes a carrier layer having a rough surface and a thin rough-surfaced etch stop layer between the carrier layer and the metal layer. The etch stop layer and wiring patterns are joined to an insulating layer such that the wiring patterns adhere to the insulating layer and the insulating layer acquires a rough surface. Thereafter, the carrier layer and the etch stop layer are removed, after which openings are formed in the insulating layer in contact with at least some of the wiring patterns. A layer of metal is electrolessly plated onto the rough major surface of the insulating layer, and then a conductive wiring pattern is selectively electroplated over the electrolessly plated layer to form plated openings that interconnect at least some of the wiring patterns.

1 . A method of manufacturing a wiring circuit element comprising the steps of:
 providing a patternable member including a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer such that corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surface of the carrier layer are rough;   etching the metal layer selectively to a material of the etch stop layer to form a plurality of wiring patterns and to expose the rough surface of the etch stop layer between the wiring patterns;   joining an insulating layer to the wiring patterns and to the exposed rough surface of the etch stop layer;   thereafter removing the carrier layer and the etch stop layer from the insulating layer to expose the wiring patterns and expose a rough major surface of the insulating layer between the wiring patterns;   forming openings in the insulating layer in contact with at least some of the wiring patterns;   electrolessly plating a layer of metal onto the rough major surface of the insulating layer and within the openings in the insulating layer;   selectively electrolytically plating a conductive wiring pattern over the electrolessly plated layer and within the openings to form plated openings which conductively interconnect at least some of the wiring patterns; and   removing portions of the electrolessly plated layer exposed by the conductive wiring pattern.   
     
     
         2 . The method as claimed in  claim 1 , wherein exposed first and second opposite surfaces of the insulating layer are joined to the wiring patterns and exposed rough surfaces of the etch stop layers of at least two of the patternable members, the step of forming openings in the insulating layer includes forming through holes extending from the first surface through the insulating layer to the second surface, and the step of selectively electrolytically plating a conductive wiring pattern conductively interconnects wiring patterns exposed at the first surface with wiring patterns exposed at the second surface of the insulating layer. 
     
     
         3 . The method as claimed in  claim 1 , wherein the etch stop layer includes a metal which is not attacked by an etchant which attacks a metal included in the metal layer overlying the etch stop layer. 
     
     
         4 . The method as claimed in  claim 3 , wherein the etch stop layer consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer consist essentially of copper. 
     
     
         5 . The method as claimed in  claim 4 , wherein the patternable member is formed by forming the thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer. 
     
     
         6 . The method as claimed in  3 , wherein the carrier layer includes a metal. 
     
     
         7 . The method as claimed in  claim 1 , wherein the exposed surface of the carrier layer in contact with the etch stop layer has unevenness of between about 0.1 micron and about 10 microns. 
     
     
         8 . The method as claimed in  claim 5 , further comprising forming a solder mask overlying surfaces of the wiring circuit element, the solder mask exposing the electrolytically plated conductive wiring patterns. 
     
     
         9 . The method as claimed in  claim 1 , wherein the wiring patterns are embedded in the insulating layer such that the rough major surface of the insulating layer is co-planar with major surfaces of the wiring patterns. 
     
     
         10 . A method of manufacturing a multi-layer wiring circuit element, comprising the steps of:
 providing a first patternable member and a second patternable member, each of the first and second patternable members including a carrier layer having a rough surface, a thin etch stop layer overlying the rough surface and a metal layer overlying the etch stop layer, such that corresponding surfaces of the etch stop layer and the metal layer overlying and adjacent to the rough surfaces of the carrier layer are rough;   etching the metal layers of the first and second patternable members selective to a material of the etch stop layer to form first wiring patterns overlying the etch stop layer of the first patternable member and to form second wiring patterns overlying the etch stop layer of the second patternable member and to expose the rough surfaces of the etch stop layers in areas exposed by the first or second wiring patterns;   joining first and second insulating layers to the wiring patterns and exposed etch stop layers of the first and second patternable members, respectively;   joining an interconnection element including at least a third insulating layer to the first and second insulating layers, the interconnection element including a plurality of interconnect wiring patterns extending in one or more directions parallel to an exposed surface of the third insulating layer;   thereafter removing the carrier layers and the etch stop layers to expose the wiring patterns joined to the first and second insulating layers and rough major surfaces of the first and second insulating layers between the wiring patterns;   forming through holes extending through the first, second and third insulating layers, the through holes contacting at least some of the wiring patterns;   electrolessly plating a layer of metal onto the rough major surfaces of the first and second insulating layers and within the through holes;   selectively electrolytically plating conductive wiring patterns over the electrolessly plated layers and within the through holes; and   removing portions of the electrolessly plated layers exposed between the electrolytically plated conductive wiring patterns.   
     
     
         11 . The method as claimed in  claim 10 , further comprising forming blind openings extending through at least one of the first and second insulating layers to the interconnect wiring patterns, wherein the step of selectively electrolytically plating conductive wiring patterns includes electrolytically plating the conductive wiring patterns in the blind openings to connect the interconnect wiring patterns with at least some of the first or second wiring patterns. 
     
     
         12 . The method as claimed in  claim 10 , wherein the interconnect wiring patterns of the interconnection element are disposed in a plurality of wiring layers separated by respective insulating layers, the interconnection element further including plated through holes conductively interconnecting the plurality of wiring layers of the interconnection element. 
     
     
         13 . The method as claimed in  claim 12 , further comprising forming a solder mask overlying surfaces of the multi-layer wiring element, the solder mask exposing the electrolytically plated conductive wiring patterns. 
     
     
         14 . The method as claimed in  claim 10 , wherein the etch stop layer of each patternable member consists essentially of nickel and the carrier layer and the metal layer overlying the etch stop layer consist essentially of copper. 
     
     
         15 . The method as claimed in  claim 14 , wherein each of the first and second patternable members is formed by forming a thin etch stop layer over the rough surface of the carrier layer and forming a second metal layer over the etch stop layer. 
     
     
         16 . The method as claimed in  13 , wherein the carrier layer of each patternable member includes a metal. 
     
     
         17 . The method as claimed in  claim 10 , wherein the carrier layer of each patternable member has unevenness of between about 0.1 micron and about 10 microns.