Semiconductor integrated circuit device and fabrication method for semiconductor integrated circuit device

Abstract

Cu interconnections embedded in an interconnection slot of a silicon oxide film are formed by polishing using CMP to improve the insulation breakdown resistance of a copper interconnection formed using the Damascene method, and after a post-CMP cleaning step, the surface of the silicon oxide film and Cu interconnections is treated by a reducing plasma (ammonia plasma). Subsequently, a continuous cap film (silicon nitride film) is formed without vacuum break.

1 . A method of fabricating a semiconductor integrated circuit device comprising:
 (a) forming a first insulating film over a semiconductor substrate;   (b) forming a groove in the second insulating film;   (c) after the step (b), performing a first plasma treatment;   (d) after the step (c), forming a barrier metal film over an inner surface of the groove and a upper surface of the first insulating film;   (e) forming a copper seed layer over the barrier metal layer;   (f) forming a copper film containing copper as its principal component on the copper seed layer so as to fill the groove;   (g) removing the barrier metal film, the copper seed layer and the copper film formed on the copper seed layer outside the groove so as to leave a copper interconnection in the groove;   (h) after the step (g), performing a second plasma treatment; and   (i) after the step (h), forming an insulating barrier film on the exposed surface of the first insulating film and the upper surface of the copper interconnection.   
   
   
       2 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein, in the step (c), the first plasma treatment is an ammonia plasma treatment.   
   
   
       3 . A method of fabricating a semiconductor integrated circuit device according to the  claim 2 ,
 wherein, in the step (c), an inner surface of the groove an upper surface of the first insulating film are nitrided by the ammonia plasma treatment.   
   
   
       4 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein, in the step (c), the first plasma treatment is an hydrogen plasma treatment.   
   
   
       5 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein, in the step (h), the second plasma treatment is an ammonia plasma treatment.   
   
   
       6 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein, in the step (h), the second plasma treatment is an hydrogen plasma treatment.   
   
   
       7 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 , further comprising a step;
 (j) after the step (f) and before the step (g), performing a hydrogen annealing treatment.   
   
   
       8 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein, in the step (f), the copper film is formed by electrolysis plating.   
   
   
       9 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein the barrier metal film includes a tantalum film.   
   
   
       10 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein the film thickness of the thinnest part of the barrier metal film in the groove is less than 10 nm.   
   
   
       11 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein the film thickness of the thinnest part of the barrier metal film in the groove is less than 5 nm.   
   
   
       12 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein, in the step (e), the copper seed layer is formed by copper sputtering with a copper target having a purity of 99.999% or more.   
   
   
       13 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein the total concentration of components other than copper in the copper interconnection, when step (h) is completed, does not exceed 0.8 At %.   
   
   
       14 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein a width of said groove is less than 0.4 μm.   
   
   
       15 . A method of fabricating a semiconductor integrated circuit device according to the  claim 1 ,
 wherein a width of said groove is less than 0.2 μm.   
   
   
       16 . (dual D) A method of fabricating a semiconductor integrated circuit device comprising:
 (a) forming a first wiring over a semiconductor substrate;   (b) forming a first insulating film over the first wiring;   (c) forming a second insulating film over the first insulting film;   (d) forming a groove in the second insulating film and a hole in the first insulating film, the hole being connected to the first wiring;   (e) after the step (d), performing a first plasma treatment;   (f) after the step (e), forming a barrier metal film over inner surfaces of the groove and the hole, over an upper surface of the second insulating film and over an upper surface of the first wiring;   (g) forming a copper seed layer over the barrier metal layer;   (h) forming a copper film containing copper as its principal component on the copper seed layer so as to fill the groove and the hole;   (i) removing the barrier metal film, the copper seed layer and the copper film formed on the copper seed layer outside the groove and the hole so as to leave a copper interconnection in the groove and the hole;   (j) after the step (i), performing a second plasma treatment; and   (k) after the step (j), forming an insulating barrier film on the exposed surface of the second insulating film and the upper surface of the copper interconnection.   
   
   
       17 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein, in the step (e), the first plasma treatment is an ammonia plasma treatment.   
   
   
       18 . A method of fabricating a semiconductor integrated circuit device according to the  claim 17 ,
 wherein, in the step (e), inner surfaces of the groove and the hole and an upper surface of the second insulating film are nitrided by the ammonia plasma treatment.   
   
   
       19 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein, in the step (e), the first plasma treatment is an hydrogen plasma treatment.   
   
   
       20 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein, in the step (j), the second plasma treatment is an ammonia plasma treatment.   
   
   
       21 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein, in the step (j), the second plasma treatment is an hydrogen plasma treatment.   
   
   
       22 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 , further comprising a step;
 (l) after the step (h) and before the step (i), performing a hydrogen annealing treatment.   
   
   
       23 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 , further comprising a step;
 (m) after the step (e) and before the step (f), removing the upper surface of the first wiring by performing a dry etching treatment.   
   
   
       24 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein, in the step (h), the copper film is formed by electrolysis plating.   
   
   
       25 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein the barrier metal film includes a tantalum film.   
   
   
       26 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein the film thickness of the thinnest part of the barrier metal film in the groove and the hole is less than 10 nm.   
   
   
       27 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein the film thickness of the thinnest part of the barrier metal film in the groove and the hole is less than 5 nm.   
   
   
       28 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein, in the step (g), the copper seed layer is formed by copper sputtering with a copper target having a purity of 99.999% or more.   
   
   
       29 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein the total concentration of components other than copper in the copper interconnection, when step (j) is completed, does not exceed 0.8 At %.   
   
   
       30 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein a width of said groove is less than 0.4 μm.   
   
   
       31 . A method of fabricating a semiconductor integrated circuit device according to the  claim 16 ,
 wherein a width of said groove is less than 0.2 μm.