Imagine sensor package and forming method of the same

Abstract

An image sensor package comprises a substrate, a chip mounted over the substrate, A molding material is formed surrounding the chip to expose a micron lens area, wherein the molding material includes via structure passing there through. A protection layer is formed on the micro lens area to prevent the micro lens. A redistributed conductive layer is formed over the molding material to connect to a pad of the chip. Metal pads are formed on via structure as connecting points with PCB. A cover layer is formed over the substrate to isolate the metal pads.

1 . A structure of image sensor package, comprising:
 a substrate;   a chip mounted over said substrate;   a molding material formed surrounding said chip to expose a micron lens area, wherein said molding material includes via structure passing there through;   a protection layer formed on said micro lens area to prevent said micro lens;   a redistributed conductive layer formed over said molding material to connect to a pad of said chip;   metal pads formed on said via structure; and   a cover layer formed over said substrate to isolate said metal pads.   
   
   
       2 . The structure in  claim 1 , wherein the material of said substrate includes metal, Alloy42 (42% Ni-58% Fe), Kovar (29% Ni-17% Co-54% Fe), glass, ceramic, silicon or PCB. 
   
   
       3 . The structure in  claim 1 , wherein said chip includes CMOS image sensor die. 
   
   
       4 . The structure in  claim 1 , wherein said chip includes CCD image sensor die. 
   
   
       5 . The structure in  claim 1 , wherein the material of said molding layer includes silicone rubber, resin, epoxy. 
   
   
       6 . The structure in  claim 1 , wherein material of said protection layer includes SiO, Al 2 O 3 , Fluoropolymer. 
   
   
       7 . The structure in  claim 1 , wherein material of said redistributed conductive layer includes Cu/Au, Cu/Ni/Au alloy. 
   
   
       8 . The structure in  claim 1 , wherein the material of said via structure includes Ti/Cu, or Ti/W/Cu alloy. 
   
   
       9 . The structure in  claim 1 , wherein the material of said cover layer includes epoxy, resin or silicone base. 
   
   
       10 . The structure in  claim 1 , further comprising BOA (Ball Grid Array) package solder balls formed on the lower surface of said substrate. 
   
   
       11 . The structure in  claim 1 , wherein said metal pads as LGA (Lane Grid Array) package pads formed on the lower surface of said substrate and peripheral of said LGA package. 
   
   
       12 . A method of making an image sensor package, comprising:
 providing a chip with a protection layer formed on a micro lens;   filling a molding material surrounding said chip;   providing a substrate mounting on said chip;   forming a first dielectric layer over said molding material and said chip, said first dielectric layer having a first opening and a second opening exposing a micro lens area formed therein;   removing partial of said first dielectric layer and said molding material to form a third opening;   forming a redistributed conductive layer over said first dielectric layer to fill into said first opening to connect pad of said chip;   forming a via structure to fill into said third opening;   forming a second dielectric layer over said first dielectric layer and said redistributed conductive layer, said second dielectric layer having a fourth opening exposing said micro lens area;   forming metal pads on said via structure;   forming a cover layer over said substrate.   
   
   
       13 . The method  claim 12 , wherein said first opening and said second opening is formed by employed a lithography process and an etching process. 
   
   
       14 . The method  claim 12 , wherein said third opening is formed by employed a lithography process and an etching process. 
   
   
       15 . The method  claim 12 , wherein said third opening is formed by employed a laser drilling process. 
   
   
       16 . The method  claim 12 , wherein said redistributed conductive layer is formed by employed an electro-plating process. 
   
   
       17 . The method  claim 12 , wherein said via structure is formed by employed an electro-plating process. 
   
   
       18 . The method  claim 12 , wherein said fourth opening is formed by employed a lithography process and an etching process. 
   
   
       19 . The method  claim 12 , further comprising a step of performing a half etching process of said substrate.