Advanced processor translation lookaside buffer management in a multithreaded system

Abstract

An advanced, processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

1 . An advanced processor, comprising:
 at least one processor configured to execute multiple threads; and   a memory management unit (MMU) coupled to the processor having first, second, and third translation-lookaside buffer (TLB) portions operable in at least two modes, each TLB portion having a plurality of entries, wherein the first TLB portion is configured for instructions, the second TLB portion is configured for data, and at least one of the plurality of entries is tagged with a thread identification.   
     
     
         2 . The advanced processor of  claim 1 , wherein:
 the at least two modes includes a partitioned mode and a global mode.   
     
     
         3 . The advanced processor of  claim 2 , wherein:
 the first and second TLB portions are configured to allow a thread to freely allocate entries in the TLB portion in either mode and to restrict access to the allocated entries to the thread in the partitioned mode; and   the third TLB portion is configured to restrict the thread to allocated entries in an exclusive subset of the third TLB portion and to restrict access to the allocated entries to the thread in the partitioned mode and to the third TLB portion is configured to allow the thread to freely allocate entries in the third TLB portion.   
     
     
         4 . The advanced processor of  claim 3 , wherein:
 the first and second TLB portions include 32 entries and the third TLB includes 128 entries.   
     
     
         5 . The advanced processor of  claim 3 , wherein:
 a not-recently-used (NRU) algorithm is used for entry allocation in the first and second TLB portions.