Method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductance

Abstract

A method and apparatus for using full-chip thermal analysis of semiconductor chip designs to compute thermal conductivity is disclosed. One embodiment of a novel method for analyzing the conductivity of a semiconductor chip design that comprises a plurality of physical layers includes defining at least one thermal layer within the plurality of physical layers, where the thermal layer(s) represents a variance in thermal conductivity relative to a remainder of the semiconductor chip design, and computing a thermal conductivity of the thermal layer(s). As the thermal layer(s) represents variances in thermal conductivity over the semiconductor chip design, the thermal layer(s) does not necessarily correspond one-to-one to the physical layers of the semiconductor chip design. Thus, the thermal conductivities within the semiconductor chip design can be computed from the thermal layers.

1 . A method for analyzing the thermal conductance of at least one semiconductor chip design, the at least one semiconductor chip design comprising a plurality of physical layers, the method comprising:
 performing full-chip thermal analysis of said at least one semiconductor chip design, the full-chip thermal analysis producing full-chip thermal gradient data;   defining a plurality of thermal layers within said at least one semiconductor chip design, in accordance with said full-chip thermal gradient data; and   computing a respective thermal conductance for each of said plurality of thermal layers.   
   
   
       2 . The method of  claim 1 , further comprising:
 iterating said performing, said defining, and said computing such that said iterating refines said respective thermal conductance for each of said plurality of thermal layers.   
   
   
       3 . The method of  claim 1 , wherein at least one of said plurality of thermal layers is further defined in accordance with at least one thermal property of at least one material contained therein. 
   
   
       4 . The method of  claim 3 , wherein said at least one thermal property comprises at least one of: a thermal conductivity of a material contained in said at least one thermal layer, a density of a material contained in said at least one thermal layer, a specific heat of a material contained in said at least one thermal layer, a thickness of a material contained in said at least one thermal layer, a cross-sectional area of a material contained in said at least one thermal layer and physical boundaries of a package incorporating said semiconductor chip design. 
   
   
       5 . The method of  claim 1 , wherein at least one boundary of at least one of said plurality of thermal layers corresponds to a boundary of at least one of the plurality of physical layers. 
   
   
       6 . The method of  claim 1 , wherein at least one boundary of at least one of said plurality of thermal layers is different from any boundary of the plurality of physical layers. 
   
   
       7 . The method of  claim 1 , wherein at least one boundary of at least one of said plurality of thermal layers extends beyond any boundary of said at least one semiconductor chip design. 
   
   
       8 . The method of  claim 1 , wherein the full-chip thermal analysis is based on at least one input, the at least one input comprising at least one of: industry standard design data pertaining to an actual chip design or a layout of the at least one semiconductor chip design or library data pertaining to semiconductor devices and interconnects incorporated in the at least one semiconductor chip design. 
   
   
       9 . The method of  claim 8 , wherein the industry standard design data comprises at least one of: electrical component extraction data, extracted parasitic data, design representation data including layout data, at least one manufacturer-specific techfile describing layer information and package models, or at least one user-generated power table including design data. 
   
   
       10 . The method of  claim 8 , wherein the library data is embodied in a library that is distributed by a semiconductor part manufacturer, distributed by a library vendor, or built by a user. 
   
   
       11 . The method of  claim 1 , wherein at least some of said plurality of thermal layers correspond to portions of the at least one semiconductor chip design in which the full-chip thermal gradient data indicates a non-uniform thermal conductance. 
   
   
       12 . A computer readable medium containing an executable program for analyzing the thermal conductance of at least one semiconductor chip design, the at least one semiconductor chip design comprising a plurality of physical layers, where the program performs the steps of
 performing full-chip thermal analysis of said at least one semiconductor chip design, the full-chip thermal analysis producing full-chip thermal gradient data;   defining a plurality of thermal layers within said at least one semiconductor chip design, in accordance with said full-chip thermal gradient data; and   computing a respective thermal conductance for each of said plurality of thermal layers.   
   
   
       13 . The computer readable medium of  claim 12 , further comprising:
 iterating said performing, said defining, and said computing such that said iterating refines said respective thermal conductance for each of said plurality of thermal layers.   
   
   
       14 . The computer readable medium of  claim 12 , wherein at least one of said plurality of thermal layers is further defined in accordance with at least one thermal property of at least one material contained therein. 
   
   
       15 . The computer readable medium of  claim 14 , wherein said at least one thermal property comprises at least one of: a thermal conductivity of a material contained in said at least one thermal layer, a density of a material contained in said at least one thermal layer, a specific heat of a material contained in said at least one thermal layer, a thickness of a material contained in said at least one thermal layer, a cross-sectional area of a material contained in said at least one thermal layer and physical boundaries of a package incorporating said semiconductor chip design. 
   
   
       16 . The computer readable medium of  claim 12 , wherein at least one boundary of at least one of said plurality of thermal layers corresponds to a boundary of at least one of the plurality of physical layers. 
   
   
       17 . The computer readable medium of  claim 12 , wherein at least one boundary of at least one of said plurality of thermal layers is different from any boundary of the plurality of physical layers. 
   
   
       18 . The computer readable medium of  claim 12 , wherein at least one boundary of at least one of said plurality of thermal layers extends beyond any boundary of said at least one semiconductor chip design. 
   
   
       19 . The computer readable medium of  claim 12 , wherein the full-chip thermal analysis is based on at least one input, the at least one input comprising at least one of: industry standard design data pertaining to an actual chip design or a layout of the at least one semiconductor chip design or library data pertaining to semiconductor devices and interconnects incorporated in the at least one semiconductor chip design. 
   
   
       20 . The computer readable medium of  claim 19 , wherein the industry standard design data comprises at least one of: electrical component extraction data, extracted parasitic data, design representation data including layout data, at least one manufacturer-specific techfile describing layer information and package models, or at least one user-generated power table including design data. 
   
   
       21 . The computer readable medium of  claim 19 , wherein the library data is embodied in a library that is distributed by a semiconductor part manufacturer, distributed by a library vendor, or built by a user. 
   
   
       22 . The computer readable medium of  claim 12 , wherein at least some of said plurality of thermal layers correspond to portions of the at least one semiconductor chip design in which the full-chip thermal gradient data indicates a non-uniform thermal conductance. 
   
   
       23 . Apparatus for analyzing the thermal conductance of at least one semiconductor chip design, the at least one semiconductor chip design comprising a plurality of physical layers, the apparatus comprising:
 means for performing full-chip thermal analysis of said at least one semiconductor chip design, the full-chip thermal analysis producing full-chip thermal gradient data;   means for defining a plurality of thermal layers within said at least one semiconductor chip design, in accordance with said full-chip thermal gradient data; and   means for computing a respective thermal conductance for each of said plurality of thermal layers.